From 1ac19e28eed4f6c53a4f295eb55500c65fc80f8d Mon Sep 17 00:00:00 2001 From: Keith Hui Date: Wed, 27 Jul 2011 23:06:16 -0400 Subject: cpu/intel/slot_1: Init L2 cache on SECC(2) CPUs. Bring from coreboot v1 support for initializing L2 cache on Slot 1 Pentium II/III CPUs, code names Klamath, Deschutes and Katmai. Build tested on ASUS P2B-LS and P3B-F. Boot tested on P2B-LS with Pentium III 600MHz, Katmai core. Also add missing include of model_68x in slot_1, to address a similar problem fixed for model_6bx by r5945. Also change Deschutes CPU init sequence to match Katmai. Change-Id: I502e8481d1a20f0a2504685e7be16b57f59c8257 Signed-off-by: Keith Hui Reviewed-on: http://review.coreboot.org/122 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer --- src/cpu/intel/slot_1/Makefile.inc | 2 ++ 1 file changed, 2 insertions(+) (limited to 'src/cpu/intel/slot_1/Makefile.inc') diff --git a/src/cpu/intel/slot_1/Makefile.inc b/src/cpu/intel/slot_1/Makefile.inc index 297ef183d9..a4de6e0b97 100644 --- a/src/cpu/intel/slot_1/Makefile.inc +++ b/src/cpu/intel/slot_1/Makefile.inc @@ -19,9 +19,11 @@ ## ramstage-y += slot_1.c +ramstage-y += l2_cache.c subdirs-y += ../model_6xx subdirs-y += ../model_65x subdirs-y += ../model_67x +subdirs-y += ../model_68x subdirs-y += ../model_6bx subdirs-y += ../../x86/tsc subdirs-y += ../../x86/mtrr -- cgit v1.2.3