From e1ec158c0a96c2bd51afa73e1bb74d64701264b0 Mon Sep 17 00:00:00 2001 From: Keith Hui Date: Fri, 5 Mar 2010 16:18:38 +0000 Subject: Add proper Slot 1 CPU support code/infrastructure. Signed-off-by: Keith Hui Acked-by: Uwe Hermann git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5187 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1 --- src/cpu/intel/slot_1/Kconfig | 33 +++++++++++++++++++++++++++++++++ 1 file changed, 33 insertions(+) create mode 100644 src/cpu/intel/slot_1/Kconfig (limited to 'src/cpu/intel/slot_1/Kconfig') diff --git a/src/cpu/intel/slot_1/Kconfig b/src/cpu/intel/slot_1/Kconfig new file mode 100644 index 0000000000..31eea999a6 --- /dev/null +++ b/src/cpu/intel/slot_1/Kconfig @@ -0,0 +1,33 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2010 Keith Hui +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +config CPU_INTEL_SLOT_1 + bool + +config DCACHE_RAM_BASE + hex + default 0xc0000 + depends on CPU_INTEL_SLOT_1 + +config DCACHE_RAM_SIZE + hex + default 0x01000 + depends on CPU_INTEL_SLOT_1 + -- cgit v1.2.3