From af8b2b91b48229d804f1f391e294467cd91adef5 Mon Sep 17 00:00:00 2001 From: Uwe Hermann Date: Fri, 15 Oct 2010 07:47:51 +0000 Subject: Drop unused DCACHE_RAM_BASE from intel/car/cache_as_ram.inc-using sockets. This CAR implementation hardcodes the Cache-as-RAM base address to: 0xd0000 - CacheSize so the DCACHE_RAM_BASE is never actually used for this implementation and these sockets. Signed-off-by: Uwe Hermann Acked-by: Peter Stuge git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5953 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1 --- src/cpu/intel/slot_1/Kconfig | 5 ----- 1 file changed, 5 deletions(-) (limited to 'src/cpu/intel/slot_1/Kconfig') diff --git a/src/cpu/intel/slot_1/Kconfig b/src/cpu/intel/slot_1/Kconfig index d10de589e7..45c94ac6f0 100644 --- a/src/cpu/intel/slot_1/Kconfig +++ b/src/cpu/intel/slot_1/Kconfig @@ -21,11 +21,6 @@ config CPU_INTEL_SLOT_1 bool select CACHE_AS_RAM -config DCACHE_RAM_BASE - hex - default 0xc0000 - depends on CPU_INTEL_SLOT_1 - config DCACHE_RAM_SIZE hex default 0x01000 -- cgit v1.2.3