From ac624a638d25645f9a9a25ee2e16224aaf921b98 Mon Sep 17 00:00:00 2001 From: Patrick Georgi Date: Tue, 9 Aug 2011 08:52:14 +0200 Subject: Crank up CPU speed on Intel Core and Core2 CPUs The CPUs start on their slowest speed, and were left that way by coreboot. This change will speed up coreboot a bit, as well as systems that don't change the clock for whatever reason. Change-Id: Ia6225eea97299a473cf50eccc6c5e7de830b1ddc Signed-off-by: Patrick Georgi Reviewed-on: http://review.coreboot.org/176 Tested-by: build bot (Jenkins) Reviewed-by: Rudolf Marek Reviewed-by: Stefan Reinauer --- src/cpu/intel/model_6fx/model_6fx_init.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) (limited to 'src/cpu/intel/model_6fx') diff --git a/src/cpu/intel/model_6fx/model_6fx_init.c b/src/cpu/intel/model_6fx/model_6fx_init.c index a3939c91f7..5cb1caed89 100644 --- a/src/cpu/intel/model_6fx/model_6fx_init.c +++ b/src/cpu/intel/model_6fx/model_6fx_init.c @@ -29,6 +29,7 @@ #include #include #include +#include #include #include #include @@ -156,6 +157,19 @@ static void configure_misc(void) msr.lo |= (1 << 20); /* Lock Enhanced SpeedStep Enable */ wrmsr(IA32_MISC_ENABLE, msr); + + // set maximum CPU speed + msr = rdmsr(IA32_PERF_STS); + int busratio_max=(msr.hi >> (40-32)) & 0x1f; + + msr = rdmsr(IA32_PLATFORM_ID); + int vid_max=msr.lo & 0x3f; + + msr.lo &= ~0xffff; + msr.lo |= busratio_max << 8; + msr.lo |= vid_max; + + wrmsr(IA32_PERF_CTL, msr); } #define PIC_SENS_CFG 0x1aa -- cgit v1.2.3