From 4f7568b126f8a51f23c994ef7b4acd24a3c64a47 Mon Sep 17 00:00:00 2001
From: Arthur Heymans <arthur@aheymans.xyz>
Date: Sat, 12 Oct 2019 17:55:49 +0200
Subject: cpu/intel/core2: Cache XIP romstage with C_ENVIRONMENT_BOOTBLOCK.

Tested on Thinkpad X200: the romstage execution speeds are back to
pre-C_ENVIRONMENT_BOOTBLOCK levels.

Change-Id: Id0b50d2f56e7cc0e055cdc8b9aa28794327eca28
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35994
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/cpu/intel/model_6fx/Kconfig | 1 +
 1 file changed, 1 insertion(+)

(limited to 'src/cpu/intel/model_6fx')

diff --git a/src/cpu/intel/model_6fx/Kconfig b/src/cpu/intel/model_6fx/Kconfig
index 32f6e8c42a..e6c82564c9 100644
--- a/src/cpu/intel/model_6fx/Kconfig
+++ b/src/cpu/intel/model_6fx/Kconfig
@@ -14,3 +14,4 @@ config CPU_INTEL_MODEL_6FX
 	select SUPPORT_CPU_UCODE_IN_CBFS
 	select CPU_INTEL_COMMON
 	select CPU_INTEL_COMMON_TIMEBASE
+	select SETUP_XIP_CACHE if C_ENVIRONMENT_BOOTBLOCK
-- 
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