From cf3076eff17dc9c152fca6ec9012e7734ff88b4c Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Tue, 10 Apr 2018 12:57:42 +0200 Subject: nb/intel/i945: Use common SMM_TSEG code Use the common SMM_TSEG code to relocate the smihandler to TSEG. This also caches the TSEG region and therefore increases MTRR usage a little in some cases. This fixes S3 resume being broken introduced by CB:25594 "sb/intel/i82801gx: Use common Intel SMM code". Currently SMRR msr's are not set on model_1067x and model_6fx since this needs the MSRR enable bit and lock set in IA32_FEATURE_CONTROL. This will be handled properly in the subsequent parallel mp init patchset. Tested on Intel d945gclf and Lenovo Thinkpad X60. Change-Id: I0e6374746c3df96ce16f1c4a177af12747d6c1a9 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/25595 Reviewed-by: Nico Huber Tested-by: build bot (Jenkins) --- src/cpu/intel/model_6ex/Makefile.inc | 1 + 1 file changed, 1 insertion(+) (limited to 'src/cpu/intel/model_6ex') diff --git a/src/cpu/intel/model_6ex/Makefile.inc b/src/cpu/intel/model_6ex/Makefile.inc index 4321f2a5f5..13e08f0ed5 100644 --- a/src/cpu/intel/model_6ex/Makefile.inc +++ b/src/cpu/intel/model_6ex/Makefile.inc @@ -1,5 +1,6 @@ ramstage-y += model_6ex_init.c subdirs-y += ../../x86/name subdirs-y += ../common +subdirs-$(CONFIG_SMM_TSEG) += ../smm/gen1 cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_6ex/microcode.bin -- cgit v1.2.3