From 2f81c03d3a0d3183061ca56aecc306995dd648f2 Mon Sep 17 00:00:00 2001 From: Sven Schnelle Date: Tue, 3 May 2011 07:55:43 +0000 Subject: Enable caching for ROM area in model_6ex/cache_as_ram.inc Signed-off-by: Sven Schnelle Acked-by: Sven Schnelle git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6554 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1 --- src/cpu/intel/model_6ex/cache_as_ram.inc | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) (limited to 'src/cpu/intel/model_6ex') diff --git a/src/cpu/intel/model_6ex/cache_as_ram.inc b/src/cpu/intel/model_6ex/cache_as_ram.inc index 0906bc0e5f..02de5ab50f 100644 --- a/src/cpu/intel/model_6ex/cache_as_ram.inc +++ b/src/cpu/intel/model_6ex/cache_as_ram.inc @@ -201,7 +201,17 @@ clear_mtrrs: xorl %edx, %edx wrmsr movl $MTRRphysMask_MSR(0), %ecx - movl $(~(1024 * 1024 - 1) | MTRRphysMaskValid), %eax + movl $(~(CONFIG_RAMTOP - 1) | MTRRphysMaskValid), %eax + movl $0x0000000f, %edx // 36bit address space + wrmsr + + /* Enable caching and Speculative Reads for the last 4MB. */ + movl $MTRRphysBase_MSR(1), %ecx + movl $(0xffc00000 | MTRR_TYPE_WRPROT), %eax + xorl %edx, %edx + wrmsr + movl $MTRRphysMask_MSR(1), %ecx + movl $(~(4 * 1024 * 1024 - 1) | MTRRphysMaskValid), %eax movl $0x0000000f, %edx // 36bit address space wrmsr -- cgit v1.2.3