From edbf5d913819726a09cd56bace2d13e74b560ab1 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Thu, 25 Jan 2018 20:03:42 +0100 Subject: cpu/intel/model_206ax: Use parallel MP init This patch adds a few southbridge calls needed for parallel MP init. Moves the smm_relocate() function to smm/gen1/smi.h, since that is where this function is defined now. Tested on Thinkpad X220, shaves off ~30ms on a 2 core, 4 threads CPU. Change-Id: Ia1d547ed4a3cb6746a0222c3e54e94e5848b0dd7 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/25618 Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- src/cpu/intel/model_206ax/Kconfig | 1 + src/cpu/intel/model_206ax/model_206ax.h | 2 +- src/cpu/intel/model_206ax/model_206ax_init.c | 155 ++++++++++++--------------- 3 files changed, 72 insertions(+), 86 deletions(-) (limited to 'src/cpu/intel/model_206ax') diff --git a/src/cpu/intel/model_206ax/Kconfig b/src/cpu/intel/model_206ax/Kconfig index b30cfa10c2..cb09d23750 100644 --- a/src/cpu/intel/model_206ax/Kconfig +++ b/src/cpu/intel/model_206ax/Kconfig @@ -23,6 +23,7 @@ config CPU_SPECIFIC_OPTIONS select TSC_SYNC_MFENCE select CPU_INTEL_COMMON select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM + select PARALLEL_MP config BOOTBLOCK_CPU_INIT string diff --git a/src/cpu/intel/model_206ax/model_206ax.h b/src/cpu/intel/model_206ax/model_206ax.h index 2bf9d32e46..f4c5d9323a 100644 --- a/src/cpu/intel/model_206ax/model_206ax.h +++ b/src/cpu/intel/model_206ax/model_206ax.h @@ -22,6 +22,7 @@ /* SandyBridge/IvyBridge bus clock is fixed at 100MHz */ #define SANDYBRIDGE_BCLK 100 +#define CORE_THREAD_COUNT_MSR 0x35 #define MSR_FEATURE_CONFIG 0x13c #define MSR_FLEX_RATIO 0x194 #define FLEX_RATIO_LOCK (1 << 20) @@ -109,7 +110,6 @@ void intel_model_206ax_finalize_smm(void); /* Configure power limits for turbo mode */ void set_power_limits(u8 power_limit_1_time); int cpu_config_tdp_levels(void); -void smm_relocate(void); #endif int get_platform_id(void); diff --git a/src/cpu/intel/model_206ax/model_206ax_init.c b/src/cpu/intel/model_206ax/model_206ax_init.c index 58aabdb198..33ad1e79ae 100644 --- a/src/cpu/intel/model_206ax/model_206ax_init.c +++ b/src/cpu/intel/model_206ax/model_206ax_init.c @@ -15,6 +15,7 @@ * GNU General Public License for more details. */ +#include #include #include #include @@ -24,6 +25,7 @@ #include #include #include +#include #include #include #include @@ -426,83 +428,6 @@ static void configure_mca(void) wrmsr(IA32_MC0_STATUS + (i * 4), msr); } -int cpu_get_apic_id_map(int *apic_id_map) -{ - struct cpuid_result result; - unsigned int threads_per_package, threads_per_core, i, shift = 0; - - /* Logical processors (threads) per core */ - result = cpuid_ext(0xb, 0); - threads_per_core = result.ebx & 0xffff; - - /* Logical processors (threads) per package */ - result = cpuid_ext(0xb, 1); - threads_per_package = result.ebx & 0xffff; - - if (threads_per_core == 1) - shift++; - - for (i = 0; i < threads_per_package && i < CONFIG_MAX_CPUS; i++) - apic_id_map[i] = i << shift; - - return threads_per_package; -} - -/* - * Initialize any extra cores/threads in this package. - */ -static void intel_cores_init(struct device *cpu) -{ - struct cpuid_result result; - unsigned int threads_per_package, threads_per_core, i; - - /* Logical processors (threads) per core */ - result = cpuid_ext(0xb, 0); - threads_per_core = result.ebx & 0xffff; - - /* Logical processors (threads) per package */ - result = cpuid_ext(0xb, 1); - threads_per_package = result.ebx & 0xffff; - - /* Only initialize extra cores from BSP */ - if (cpu->path.apic.apic_id) - return; - - printk(BIOS_DEBUG, "CPU: %u has %u cores, %u threads per core\n", - cpu->path.apic.apic_id, threads_per_package/threads_per_core, - threads_per_core); - - for (i = 1; i < threads_per_package; ++i) { - struct device_path cpu_path; - struct device *new; - - /* Build the CPU device path */ - cpu_path.type = DEVICE_PATH_APIC; - cpu_path.apic.apic_id = - cpu->path.apic.apic_id + i; - - /* Update APIC ID if no hyperthreading */ - if (threads_per_core == 1) - cpu_path.apic.apic_id <<= 1; - - /* Allocate the new CPU device structure */ - new = alloc_dev(cpu->bus, &cpu_path); - if (!new) - continue; - - printk(BIOS_DEBUG, "CPU: %u has core %u\n", - cpu->path.apic.apic_id, - new->path.apic.apic_id); - - /* Start the new CPU */ - if (is_smp_boot() && !start_cpu(new)) { - /* Record the error in cpu? */ - printk(BIOS_ERR, "CPU %u would not start!\n", - new->path.apic.apic_id); - } - } -} - static void model_206ax_report(void) { static const char *const mode[] = {"NOT ", ""}; @@ -536,18 +461,12 @@ static void model_206ax_init(struct device *cpu) /* Turn on caching if we haven't already */ x86_enable_cache(); - intel_update_microcode_from_cbfs(); - /* Clear out pending MCEs */ configure_mca(); /* Print infos */ model_206ax_report(); - /* Setup MTRRs based on physical address size */ - x86_setup_mtrrs_with_detect(); - x86_mtrr_check(); - /* Setup Page Attribute Tables (PAT) */ // TODO set up PAT @@ -578,9 +497,75 @@ static void model_206ax_init(struct device *cpu) /* Enable Turbo */ enable_turbo(); +} + +/* MP initialization support. */ +static const void *microcode_patch; - /* Start up extra cores */ - intel_cores_init(cpu); +static void pre_mp_init(void) +{ + /* Setup MTRRs based on physical address size. */ + x86_setup_mtrrs_with_detect(); + x86_mtrr_check(); +} + +static int get_cpu_count(void) +{ + msr_t msr; + int num_threads; + int num_cores; + + msr = rdmsr(CORE_THREAD_COUNT_MSR); + num_threads = (msr.lo >> 0) & 0xffff; + num_cores = (msr.lo >> 16) & 0xffff; + printk(BIOS_DEBUG, "CPU has %u cores, %u threads enabled.\n", + num_cores, num_threads); + + return num_threads; +} + +static void get_microcode_info(const void **microcode, int *parallel) +{ + microcode_patch = intel_microcode_find(); + *microcode = microcode_patch; + *parallel = 1; +} + +static void per_cpu_smm_trigger(void) +{ + /* Relocate the SMM handler. */ + smm_relocate(); + + /* After SMM relocation a 2nd microcode load is required. */ + intel_microcode_load_unlocked(microcode_patch); +} + +static void post_mp_init(void) +{ + /* Now that all APs have been relocated as well as the BSP let SMIs + * start flowing. */ + southbridge_smm_init(); + + /* Lock down the SMRAM space. */ + smm_lock(); +} + + +static const struct mp_ops mp_ops = { + .pre_mp_init = pre_mp_init, + .get_cpu_count = get_cpu_count, + .get_smm_info = smm_info, + .get_microcode_info = get_microcode_info, + .pre_mp_smm_init = smm_initialize, + .per_cpu_smm_trigger = per_cpu_smm_trigger, + .relocation_handler = smm_relocation_handler, + .post_mp_init = post_mp_init, +}; + +void bsp_init_and_start_aps(struct bus *cpu_bus) +{ + if (mp_init_with_smm(cpu_bus, &mp_ops)) + printk(BIOS_ERR, "MP initialization failure.\n"); } static struct device_operations cpu_dev_ops = { -- cgit v1.2.3