From dd4d8951368029634f53e44e1a222417b72036c0 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Sun, 3 Jun 2018 12:04:26 +0200 Subject: cpu/intel/car/non-evict: Prepare for some POSTCAR_STAGE support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Prepare a common cache as ram for CPU's featuring a Non eviction mode MSR. Change-Id: I7fa3853498856050855b3b97546f4d31f66d12f7 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/26789 Reviewed-by: Kyösti Mälkki Tested-by: build bot (Jenkins) --- src/cpu/intel/model_206ax/Makefile.inc | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'src/cpu/intel/model_206ax') diff --git a/src/cpu/intel/model_206ax/Makefile.inc b/src/cpu/intel/model_206ax/Makefile.inc index 1e04554655..0e2733e279 100644 --- a/src/cpu/intel/model_206ax/Makefile.inc +++ b/src/cpu/intel/model_206ax/Makefile.inc @@ -17,5 +17,11 @@ ramstage-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_206ax/microcode.bin cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_306ax/microcode.bin +ifneq ($(CONFIG_POSTCAR_STAGE),y) cpu_incs-y += $(src)/cpu/intel/model_206ax/cache_as_ram.inc +else +cpu_incs-y += $(src)/cpu/intel/car/non-evict/cache_as_ram.S +postcar-y += ../car/non-evict/exit_car.S +endif + romstage-y += ../car/romstage.c -- cgit v1.2.3