From c65a36eb0f097ca13cdab8a787ce5cf35f49a64f Mon Sep 17 00:00:00 2001
From: Stefan Reinauer <reinauer@chromium.org>
Date: Tue, 10 Jul 2012 17:02:21 -0700
Subject: Enable Microcode in CBFS for all SandyBridge/IvyBridge systems

Change-Id: Idee4facc18e0be60906d2a2f0e99bd39de8d7247
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1332
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
---
 src/cpu/intel/model_206ax/bootblock.c | 10 ----------
 1 file changed, 10 deletions(-)

(limited to 'src/cpu/intel/model_206ax/bootblock.c')

diff --git a/src/cpu/intel/model_206ax/bootblock.c b/src/cpu/intel/model_206ax/bootblock.c
index dbc35914cb..02958bbc85 100644
--- a/src/cpu/intel/model_206ax/bootblock.c
+++ b/src/cpu/intel/model_206ax/bootblock.c
@@ -25,12 +25,6 @@
 #include <arch/io.h>
 #include <arch/romcc_io.h>
 
-#if !CONFIG_MICROCODE_IN_CBFS
-static const uint32_t microcode_updates[] = {
-	#include "microcode_blob.h"
-};
-#endif
-
 #include <cpu/intel/microcode/microcode.c>
 #include "model_206ax.h"
 
@@ -125,9 +119,5 @@ static void bootblock_cpu_init(void)
 	/* Set flex ratio and reset if needed */
 	set_flex_ratio_to_tdp_nominal();
 	enable_rom_caching();
-#if CONFIG_MICROCODE_IN_CBFS
 	intel_update_microcode_from_cbfs();
-#else
-	intel_update_microcode(microcode_updates);
-#endif
 }
-- 
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