From bbf013c38fe76cf9cc107c41c17e4ac432847d28 Mon Sep 17 00:00:00 2001 From: Kyösti Mälkki Date: Mon, 6 Jan 2014 11:08:01 +0200 Subject: nehalem/sandy/ivy/haswell: Enable WRPROT cache for all of flash MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit CBFS could start from below 4MB, and should be cacheable for the purpose of early microcode update and CBFS search for romstage file. Change-Id: Ia2a1c6e5fdcc3201fafc8cf5c841cebbbf0b30c9 Signed-off-by: Kyösti Mälkki Reviewed-on: http://review.coreboot.org/4626 Tested-by: build bot (Jenkins) Reviewed-by: Vladimir Serbinenko Reviewed-by: Paul Menzel Reviewed-by: Aaron Durbin --- src/cpu/intel/model_206ax/bootblock.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/cpu/intel/model_206ax/bootblock.c') diff --git a/src/cpu/intel/model_206ax/bootblock.c b/src/cpu/intel/model_206ax/bootblock.c index d3579f7471..49c4012eee 100644 --- a/src/cpu/intel/model_206ax/bootblock.c +++ b/src/cpu/intel/model_206ax/bootblock.c @@ -54,7 +54,7 @@ static void enable_rom_caching(void) msr_t msr; disable_cache(); - set_var_mtrr(1, 0xffc00000, 4*1024*1024, MTRR_TYPE_WRPROT); + set_var_mtrr(1, CACHE_ROM_BASE, CACHE_ROM_SIZE, MTRR_TYPE_WRPROT); enable_cache(); /* Enable Variable MTRRs */ -- cgit v1.2.3