From c16e9dfa18cb37b40ef7eef87f22385215b04ec2 Mon Sep 17 00:00:00 2001 From: Vladimir Serbinenko Date: Fri, 29 May 2015 16:18:01 +0200 Subject: Create i945-ivy smm tseg init based on ivy code. CPU-side logic is unchanged for this range of CPUs as long as all of them use TSEG (or ASEG, just needs to be consistent). So uplift 206ax code while extracting southbridge and APIC code into separate functions. Change-Id: Ib365681d1da8115922c557fddcc59afc156826da Signed-off-by: Vladimir Serbinenko Reviewed-on: http://review.coreboot.org/10465 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: Alexandru Gagniuc --- src/cpu/intel/model_206ax/Makefile.inc | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) (limited to 'src/cpu/intel/model_206ax/Makefile.inc') diff --git a/src/cpu/intel/model_206ax/Makefile.inc b/src/cpu/intel/model_206ax/Makefile.inc index c296fd9fd5..6e0dcf61a9 100644 --- a/src/cpu/intel/model_206ax/Makefile.inc +++ b/src/cpu/intel/model_206ax/Makefile.inc @@ -1,5 +1,6 @@ ramstage-y += model_206ax_init.c subdirs-y += ../../x86/name +subdirs-y += ../smm/gen1 ramstage-y += acpi.c @@ -8,5 +9,3 @@ smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c cpu_incs += $(src)/cpu/intel/model_206ax/cache_as_ram.inc - -ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smmrelocate.c -- cgit v1.2.3