From 67031a565b3179fa5a28282fc2e24b47d16003e8 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Mon, 5 Feb 2018 19:08:03 +0100 Subject: cpu/intel/sandybridge: Put stage cache into TSEG TSEG is not accessible in ring 0 after it is locked in ramstage, in contrast with cbmem which remains accessible. Assuming SMM does not touch the cache this is a good region to cache stages. The code is mostly copied from src/cpu/intel/haswell. TESTED on Thinkpad X220: on a cold boot the stage cache gets created and on S3 the cached ramstage gets properly used. Change-Id: Ifd8f939416b1712f6e5c74f544a5828745f8c2f2 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/23592 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/cpu/intel/model_206ax/Kconfig | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'src/cpu/intel/model_206ax/Kconfig') diff --git a/src/cpu/intel/model_206ax/Kconfig b/src/cpu/intel/model_206ax/Kconfig index f16b11962c..b30cfa10c2 100644 --- a/src/cpu/intel/model_206ax/Kconfig +++ b/src/cpu/intel/model_206ax/Kconfig @@ -22,6 +22,7 @@ config CPU_SPECIFIC_OPTIONS #select AP_IN_SIPI_WAIT select TSC_SYNC_MFENCE select CPU_INTEL_COMMON + select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM config BOOTBLOCK_CPU_INIT string @@ -35,4 +36,13 @@ config SMM_TSEG_SIZE hex default 0x800000 +config SMM_RESERVED_SIZE + hex + default 0x100000 + +# Intel Enhanced Debug region must be 4MB +config IED_REGION_SIZE + hex + default 0x400000 + endif -- cgit v1.2.3