From 3c0c3619bcd0c6d25bdf5492be6ba8bb2d5bb410 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= <kyosti.malkki@gmail.com>
Date: Sun, 23 Dec 2018 07:43:01 +0200
Subject: arch/x86: SSE2 implies SSE support
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Change-Id: Ic9ffcfadd0cd41bb033ed2aec9fb98009dd62383
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30394
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
---
 src/cpu/intel/model_2065x/Kconfig | 1 -
 1 file changed, 1 deletion(-)

(limited to 'src/cpu/intel/model_2065x')

diff --git a/src/cpu/intel/model_2065x/Kconfig b/src/cpu/intel/model_2065x/Kconfig
index 59bb8d8b86..9481917ff8 100644
--- a/src/cpu/intel/model_2065x/Kconfig
+++ b/src/cpu/intel/model_2065x/Kconfig
@@ -10,7 +10,6 @@ config CPU_SPECIFIC_OPTIONS
 	select ARCH_ROMSTAGE_X86_32
 	select ARCH_RAMSTAGE_X86_32
 	select SMP
-	select SSE
 	select SSE2
 	select UDELAY_TSC
 	select TSC_CONSTANT_RATE
-- 
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