From 4e6b7907de07c9c7d4b01a6213a8e13e946398cb Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Tue, 2 Oct 2018 08:44:47 +0200 Subject: src: Fix MSR_PKG_CST_CONFIG_CONTROL register name Change-Id: I492224b6900b9658d54c8cf486ef5d64b299687f Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/28871 Tested-by: build bot (Jenkins) Reviewed-by: Lijian Zhao --- src/cpu/intel/model_2065x/finalize.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/cpu/intel/model_2065x/finalize.c') diff --git a/src/cpu/intel/model_2065x/finalize.c b/src/cpu/intel/model_2065x/finalize.c index 8425f6afe6..08541c0d89 100644 --- a/src/cpu/intel/model_2065x/finalize.c +++ b/src/cpu/intel/model_2065x/finalize.c @@ -46,7 +46,7 @@ static void msr_set_bit(unsigned int reg, unsigned int bit) void intel_model_2065x_finalize_smm(void) { /* Lock C-State MSR */ - msr_set_bit(MSR_PMG_CST_CONFIG_CONTROL, 15); + msr_set_bit(MSR_PKG_CST_CONFIG_CONTROL, 15); /* Lock AES-NI only if supported */ if (cpuid_ecx(1) & (1 << 25)) -- cgit v1.2.3