From 22dcdd914cf36ce657f5e72c975a96d577400a69 Mon Sep 17 00:00:00 2001 From: Vladimir Serbinenko Date: Thu, 6 Jun 2013 22:10:45 +0200 Subject: Add support for Intel Nehalem CPU Change-Id: I7ecc394b1e5bc0b8b85a8afac22efc0befe2d36a Signed-off-by: Vladimir Serbinenko Signed-off-by: Stefan Reinauer Reviewed-on: http://review.coreboot.org/3395 Reviewed-by: Alexandru Gagniuc Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer --- src/cpu/intel/model_2065x/finalize.c | 73 ++++++++++++++++++++++++++++++++++++ 1 file changed, 73 insertions(+) create mode 100644 src/cpu/intel/model_2065x/finalize.c (limited to 'src/cpu/intel/model_2065x/finalize.c') diff --git a/src/cpu/intel/model_2065x/finalize.c b/src/cpu/intel/model_2065x/finalize.c new file mode 100644 index 0000000000..b37a84cfe7 --- /dev/null +++ b/src/cpu/intel/model_2065x/finalize.c @@ -0,0 +1,73 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 The Chromium OS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include +#include "model_2065x.h" + +static void msr_set_bit(unsigned reg, unsigned bit) +{ + msr_t msr = rdmsr(reg); + + if (bit < 32) { + if (msr.lo & (1 << bit)) + return; + msr.lo |= 1 << bit; + } else { + if (msr.hi & (1 << (bit - 32))) + return; + msr.hi |= 1 << (bit - 32); + } + + wrmsr(reg, msr); +} + +void intel_model_2065x_finalize_smm(void) +{ + msr_set_bit(MSR_PMG_CST_CONFIG_CONTROL, 15); + + /* Lock AES-NI only if supported */ + if (cpuid_ecx(1) & (1 << 25)) + msr_set_bit(MSR_FEATURE_CONFIG, 0); + +#ifdef LOCK_POWER_CONTROL_REGISTERS + /* + * Lock the power control registers. + * + * These registers can be left unlocked if modifying power + * limits from the OS is desirable. Modifying power limits + * from the OS can be especially useful for experimentation + * during early phases of system bringup while the thermal + * power envelope is being proven. + */ + + msr_set_bit(MSR_PP0_CURRENT_CONFIG, 31); + msr_set_bit(MSR_PP1_CURRENT_CONFIG, 31); + msr_set_bit(MSR_PKG_POWER_LIMIT, 63); + msr_set_bit(MSR_PP0_POWER_LIMIT, 31); + msr_set_bit(MSR_PP1_POWER_LIMIT, 31); +#endif + + msr_set_bit(MSR_MISC_PWR_MGMT, 22); + msr_set_bit(MSR_LT_LOCK_MEMORY, 0); +} -- cgit v1.2.3