From 97c7c6bbb6c9dd2ef4f917c3c4c16a8ff0de5d9f Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Tue, 15 May 2018 16:45:21 +0200 Subject: cpu/intel/model_2065x: Put stage cache in TSEG TSEG is not accessible in ring 0 after it is locked in ramstage, in contrast with cbmem which remains accessible. Assuming SMM does not touch the cache this is a good region to cache stages. Change-Id: I89cbfb6ece62f554ac676fe686115e841d2c1e40 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/26298 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Rudolph --- src/cpu/intel/model_2065x/Kconfig | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'src/cpu/intel/model_2065x/Kconfig') diff --git a/src/cpu/intel/model_2065x/Kconfig b/src/cpu/intel/model_2065x/Kconfig index 707713c697..d8c016867c 100644 --- a/src/cpu/intel/model_2065x/Kconfig +++ b/src/cpu/intel/model_2065x/Kconfig @@ -21,6 +21,7 @@ config CPU_SPECIFIC_OPTIONS select CPU_INTEL_COMMON select NO_FIXED_XIP_ROM_SIZE select PARALLEL_MP + select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM config BOOTBLOCK_CPU_INIT string @@ -30,4 +31,8 @@ config SMM_TSEG_SIZE hex default 0x800000 +config SMM_RESERVED_SIZE + hex + default 0x100000 + endif -- cgit v1.2.3