From ae7d6ef8b7ef5ca9c04d8d929332d18d563f723e Mon Sep 17 00:00:00 2001 From: Kyösti Mälkki Date: Thu, 28 Jun 2012 21:50:43 +0300 Subject: Intel model_106cx: change CAR to model_6ex MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Diff between model_106cx and model_6ex CAR codes suggests currently used model_106cx CAR is not optimal - destination RAM and source ROM of ramstage copy_and_run are only partly set cacheable. It appears variable MTRR setting for XIP cache is left enabled on model_106cx code, where it should have extended to cover all of Flash. Introduces untested functional change on boards: intel/d945gclf iwave/iWRainbowG6 Deletes file: model_106cx/cache_as_ram.inc Change-Id: I35229f8433927e83821e72e9d9a9fc8fb09c3f1d Signed-off-by: Kyösti Mälkki Reviewed-on: http://review.coreboot.org/642 Tested-by: build bot (Jenkins) Reviewed-by: Sven Schnelle --- src/cpu/intel/model_106cx/Makefile.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/cpu/intel/model_106cx/Makefile.inc') diff --git a/src/cpu/intel/model_106cx/Makefile.inc b/src/cpu/intel/model_106cx/Makefile.inc index edcd01c765..018febc621 100644 --- a/src/cpu/intel/model_106cx/Makefile.inc +++ b/src/cpu/intel/model_106cx/Makefile.inc @@ -1,4 +1,4 @@ driver-y += model_106cx_init.c subdirs-y += ../../x86/name -cpu_incs += $(src)/cpu/intel/model_106cx/cache_as_ram.inc +cpu_incs += $(src)/cpu/intel/model_6ex/cache_as_ram.inc -- cgit v1.2.3