From 9ed1456eff73d1a268eabb84176dd2a2107bf2d7 Mon Sep 17 00:00:00 2001 From: Kyösti Mälkki Date: Wed, 27 Jun 2012 16:14:49 +0300 Subject: Intel CPUs: execute microcode update only once per core MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Early HT-enabled CPUs do not serialize microcode updates within a core. Solve this by running microcode updates on the thread with the smallest lapic ID of a core only. Also set MTRRs once per core only. Change-Id: I6a3cc9ecec2d8e0caed29605a9b19ec35a817620 Signed-off-by: Kyösti Mälkki Reviewed-on: http://review.coreboot.org/1142 Tested-by: build bot (Jenkins) Reviewed-by: Sven Schnelle Reviewed-by: Stefan Reinauer --- src/cpu/intel/hyperthreading/intel_sibling.c | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) (limited to 'src/cpu/intel/hyperthreading/intel_sibling.c') diff --git a/src/cpu/intel/hyperthreading/intel_sibling.c b/src/cpu/intel/hyperthreading/intel_sibling.c index 2d2e105f8d..b9a9ae7bb1 100644 --- a/src/cpu/intel/hyperthreading/intel_sibling.c +++ b/src/cpu/intel/hyperthreading/intel_sibling.c @@ -14,6 +14,27 @@ static int first_time = 1; static int disable_siblings = !CONFIG_LOGICAL_CPUS; +/* Return true if running thread does not have the smallest lapic ID + * within a CPU core. + */ +int intel_ht_sibling(void) +{ + unsigned int core_ids, apic_ids, threads; + + apic_ids = 1; + if (cpuid_eax(0) >= 1) + apic_ids = (cpuid_ebx(1) >> 16) & 0xff; + if (apic_ids < 1) + apic_ids = 1; + + core_ids = 1; + if (cpuid_eax(0) >= 4) + core_ids += (cpuid_eax(4) >> 26) & 0x3f; + + threads = (apic_ids / core_ids); + return !!(lapicid() & (threads-1)); +} + void intel_sibling_init(device_t cpu) { unsigned i, siblings; -- cgit v1.2.3