From ece26961b9fadbec5e7424bd91f10f600430e975 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Tue, 7 Aug 2018 12:24:16 +0200 Subject: src/cpu: Fix typo Change-Id: I13dec72b2de2a525d45909e697c33fbdc31111cb Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/27918 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth --- src/cpu/intel/haswell/finalize.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/cpu/intel/haswell') diff --git a/src/cpu/intel/haswell/finalize.c b/src/cpu/intel/haswell/finalize.c index ba2538702e..ce22e629e8 100644 --- a/src/cpu/intel/haswell/finalize.c +++ b/src/cpu/intel/haswell/finalize.c @@ -72,7 +72,7 @@ void intel_cpu_haswell_finalize_smm(void) msr_set_bit(MSR_PP1_POWER_LIMIT, 31); #endif - /* Lock TM interupts - route thermal events to all processors */ + /* Lock TM interrupts - route thermal events to all processors */ msr_set_bit(MSR_MISC_PWR_MGMT, 22); /* Lock memory configuration to protect SMM */ -- cgit v1.2.3