From 3d78ece7d02797187a56ada8ba8ae379df4a5b95 Mon Sep 17 00:00:00 2001 From: Stefan Reinauer Date: Mon, 16 Mar 2015 16:53:27 -0700 Subject: haswell: Fix monotonic timer integration In some previous attempt to enable monotonic timers on all platforms, the LAPIC monotonic timer was selected for Haswell devices, despite the fact that LAPIC timers are not used in coreboot on Haswell (See haswell Kconfig) and there already was a monotonic timer implementation enabled that just needed to be added for SMM as well. Change-Id: I6beb2977864e507956636860ed463e1991cea1ed Signed-off-by: Stefan Reinauer Reviewed-on: http://review.coreboot.org/8702 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/cpu/intel/haswell/Kconfig | 1 - src/cpu/intel/haswell/Makefile.inc | 1 + 2 files changed, 1 insertion(+), 1 deletion(-) (limited to 'src/cpu/intel/haswell') diff --git a/src/cpu/intel/haswell/Kconfig b/src/cpu/intel/haswell/Kconfig index 4732623e26..741b6770ec 100644 --- a/src/cpu/intel/haswell/Kconfig +++ b/src/cpu/intel/haswell/Kconfig @@ -25,7 +25,6 @@ config CPU_SPECIFIC_OPTIONS select CPU_INTEL_FIRMWARE_INTERFACE_TABLE select PARALLEL_CPU_INIT select PARALLEL_MP - select LAPIC_MONOTONIC_TIMER config BOOTBLOCK_CPU_INIT string diff --git a/src/cpu/intel/haswell/Makefile.inc b/src/cpu/intel/haswell/Makefile.inc index 2518e9a72e..82d3beccdd 100644 --- a/src/cpu/intel/haswell/Makefile.inc +++ b/src/cpu/intel/haswell/Makefile.inc @@ -11,5 +11,6 @@ cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c smm-$(CONFIG_HAVE_SMI_HANDLER) += tsc_freq.c +smm-$(CONFIG_MONOTONIC_TIMER_MSR) += monotonic_timer.c cpu_incs += $(src)/cpu/intel/haswell/cache_as_ram.inc -- cgit v1.2.3