From 157b189f6b97b6e9ecd8d29edbbd045fbbc231f5 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Fri, 16 Aug 2019 14:02:25 +0300 Subject: cpu/intel: Enter romstage without BIST MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit When entry to romstage is via cpu/intel/car/romstage.c BIST has not been passed down the path for sometime. Change-Id: I345975c53014902269cee21fc393331d33a84dce Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/34908 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans --- src/cpu/intel/haswell/haswell.h | 1 - src/cpu/intel/haswell/romstage.c | 6 +----- 2 files changed, 1 insertion(+), 6 deletions(-) (limited to 'src/cpu/intel/haswell') diff --git a/src/cpu/intel/haswell/haswell.h b/src/cpu/intel/haswell/haswell.h index 819c2e44f3..4b5a3b094a 100644 --- a/src/cpu/intel/haswell/haswell.h +++ b/src/cpu/intel/haswell/haswell.h @@ -141,7 +141,6 @@ struct romstage_params { struct pei_data *pei_data; const void *gpio_map; const struct rcba_config_instruction *rcba_config; - unsigned long bist; void (*copy_spd)(struct pei_data *); }; void romstage_common(const struct romstage_params *params); diff --git a/src/cpu/intel/haswell/romstage.c b/src/cpu/intel/haswell/romstage.c index 544a93fd97..43f5109889 100644 --- a/src/cpu/intel/haswell/romstage.c +++ b/src/cpu/intel/haswell/romstage.c @@ -33,14 +33,10 @@ void romstage_common(const struct romstage_params *params) int boot_mode; int wake_from_s3; - if (params->bist == 0) - enable_lapic(); + enable_lapic(); wake_from_s3 = early_pch_init(params->gpio_map, params->rcba_config); - /* Halt if there was a built in self test failure */ - report_bist_failure(params->bist); - /* Perform some early chipset initialization required * before RAM initialization can work */ -- cgit v1.2.3