From 1515a48cffbb14328e0f68850f60a10332043087 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Sun, 13 Jun 2021 22:33:06 +0200 Subject: cpu/intel/haswell: Enable MCA logging Intel document 493770 (Haswell BIOS Writer's Guide) revision 1.8.0 recommends writing all ones to the IA32_MCi_CTL registers in order to enable all MCA error reporting. Change-Id: Ib5d2c759483026b5b4804c5a4b2b969d2269af22 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/55463 Reviewed-by: Arthur Heymans Tested-by: build bot (Jenkins) --- src/cpu/intel/haswell/haswell_init.c | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'src/cpu/intel/haswell') diff --git a/src/cpu/intel/haswell/haswell_init.c b/src/cpu/intel/haswell/haswell_init.c index 8ba1c937f0..9fcb527a16 100644 --- a/src/cpu/intel/haswell/haswell_init.c +++ b/src/cpu/intel/haswell/haswell_init.c @@ -524,6 +524,12 @@ static void configure_mca(void) msr = rdmsr(IA32_MCG_CAP); num_banks = msr.lo & 0xff; + + /* Enable all error reporting */ + msr.lo = msr.hi = ~0; + for (i = 0; i < num_banks; i++) + wrmsr(IA32_MC0_CTL + (i * 4), msr); + msr.lo = msr.hi = 0; /* TODO(adurbin): This should only be done on a cold boot. Also, some * of these banks are core vs package scope. For now every CPU clears -- cgit v1.2.3