From 825646e6431b51bd45349dbd2cb1d607e2eecae1 Mon Sep 17 00:00:00 2001 From: Kyösti Mälkki Date: Fri, 2 Aug 2019 06:14:50 +0300 Subject: intel/haswell: Move stage_cache support function MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Let garbage-collection take care of stage_cache_external_region() if it is no needed and move implementation to a suitable file already building for needed stages. Remove aliasing CONFIG_RESERVED_SMM_SIZE as RESERVED_SMM_SIZE. Change-Id: Ie6fcc40fba14575e8ee058f45a1a359a05f00aca Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/34668 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans --- src/cpu/intel/haswell/smmrelocate.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/cpu/intel/haswell/smmrelocate.c') diff --git a/src/cpu/intel/haswell/smmrelocate.c b/src/cpu/intel/haswell/smmrelocate.c index 3948cfe519..3a4a0a7830 100644 --- a/src/cpu/intel/haswell/smmrelocate.c +++ b/src/cpu/intel/haswell/smmrelocate.c @@ -250,7 +250,7 @@ static void fill_in_relocation_params(struct device *dev, params->ied_size = tseg_size - params->smram_size; /* Adjust available SMM handler memory size. */ - params->smram_size -= RESERVED_SMM_SIZE; + params->smram_size -= CONFIG_SMM_RESERVED_SIZE; /* SMRR has 32-bits of valid address aligned to 4KiB. */ params->smrr_base.lo = (params->smram_base & rmask) | MTRR_TYPE_WRBACK; -- cgit v1.2.3