From e1e87e0ed6280f168abd92edcd692aec4ead8fe8 Mon Sep 17 00:00:00 2001 From: Duncan Laurie Date: Fri, 26 Apr 2013 10:35:19 -0700 Subject: haswell: Configure PCH power sharing for ULT This reads PCH power levels via PCODE mailbox and writes the values into the PMSYNC registers as indicated in the BWG. Change-Id: Iddcdef9b7deb6365f874f629599d1f7376c9a190 Signed-off-by: Duncan Laurie Reviewed-on: https://gerrit.chromium.org/gerrit/49329 Reviewed-by: Aaron Durbin Reviewed-on: http://review.coreboot.org/4143 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc --- src/cpu/intel/haswell/haswell.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'src/cpu/intel/haswell/haswell.h') diff --git a/src/cpu/intel/haswell/haswell.h b/src/cpu/intel/haswell/haswell.h index 96f94ebd0a..7dfba863d4 100644 --- a/src/cpu/intel/haswell/haswell.h +++ b/src/cpu/intel/haswell/haswell.h @@ -107,6 +107,8 @@ #define MAILBOX_BIOS_CMD_WRITE_PCS 2 #define MAILBOX_BIOS_CMD_READ_CALIBRATION 0x509 #define MAILBOX_BIOS_CMD_FSM_MEASURE_INTVL 0x909 +#define MAILBOX_BIOS_CMD_READ_PCH_POWER 0xa +#define MAILBOX_BIOS_CMD_READ_PCH_POWER_EXT 0xb /* Errors are returned back in bits 7:0. */ #define MAILBOX_BIOS_ERROR_NONE 0 #define MAILBOX_BIOS_ERROR_INVALID_COMMAND 1 -- cgit v1.2.3