From 76c3700f02f79b49fec30d6ef18d336f122cbf50 Mon Sep 17 00:00:00 2001 From: Aaron Durbin Date: Tue, 30 Oct 2012 09:03:43 -0500 Subject: haswell: Add initial support for Haswell platforms The Haswell parts use a PCH code named Lynx Point (Series 8). Therefore, the southbridge support is included as well. The basis for this code is the Sandybridge code. Management Engine, IRQ routing, and ACPI still requires more attention, but this is a good starting point. This code partially gets up through the romstage just before training memory on a Haswell reference board. Change-Id: If572d6c21ca051b486b82a924ca0ffe05c4d0ad4 Signed-off-by: Aaron Durbin Reviewed-on: http://review.coreboot.org/2616 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich --- src/cpu/intel/haswell/chip.h | 39 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 39 insertions(+) create mode 100644 src/cpu/intel/haswell/chip.h (limited to 'src/cpu/intel/haswell/chip.h') diff --git a/src/cpu/intel/haswell/chip.h b/src/cpu/intel/haswell/chip.h new file mode 100644 index 0000000000..52020437f9 --- /dev/null +++ b/src/cpu/intel/haswell/chip.h @@ -0,0 +1,39 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +extern struct chip_operations cpu_intel_haswell_ops; + +/* Magic value used to locate this chip in the device tree */ +#define SPEEDSTEP_APIC_MAGIC 0xACAC + +struct cpu_intel_haswell_config { + u8 disable_acpi; /* Do not generate CPU ACPI tables */ + + u8 pstate_coord_type; /* Processor Coordination Type */ + + int c1_battery; /* ACPI C1 on Battery Power */ + int c2_battery; /* ACPI C2 on Battery Power */ + int c3_battery; /* ACPI C3 on Battery Power */ + + int c1_acpower; /* ACPI C1 on AC Power */ + int c2_acpower; /* ACPI C2 on AC Power */ + int c3_acpower; /* ACPI C3 on AC Power */ + + int tcc_offset; /* TCC Activation Offset */ +}; -- cgit v1.2.3