From 76c3700f02f79b49fec30d6ef18d336f122cbf50 Mon Sep 17 00:00:00 2001 From: Aaron Durbin Date: Tue, 30 Oct 2012 09:03:43 -0500 Subject: haswell: Add initial support for Haswell platforms The Haswell parts use a PCH code named Lynx Point (Series 8). Therefore, the southbridge support is included as well. The basis for this code is the Sandybridge code. Management Engine, IRQ routing, and ACPI still requires more attention, but this is a good starting point. This code partially gets up through the romstage just before training memory on a Haswell reference board. Change-Id: If572d6c21ca051b486b82a924ca0ffe05c4d0ad4 Signed-off-by: Aaron Durbin Reviewed-on: http://review.coreboot.org/2616 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich --- src/cpu/intel/haswell/Makefile.inc | 10 ++++++++++ 1 file changed, 10 insertions(+) create mode 100644 src/cpu/intel/haswell/Makefile.inc (limited to 'src/cpu/intel/haswell/Makefile.inc') diff --git a/src/cpu/intel/haswell/Makefile.inc b/src/cpu/intel/haswell/Makefile.inc new file mode 100644 index 0000000000..467c948430 --- /dev/null +++ b/src/cpu/intel/haswell/Makefile.inc @@ -0,0 +1,10 @@ +ramstage-y += haswell_init.c +subdirs-y += ../../x86/name + +ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += acpi.c + +cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c + +smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c + +cpu_incs += $(src)/cpu/intel/haswell/cache_as_ram.inc -- cgit v1.2.3