From cdc50480c414df3b5f438f7f26a73df597e544ae Mon Sep 17 00:00:00 2001 From: Lee Leahy Date: Wed, 15 Mar 2017 18:26:18 -0700 Subject: cpu/intel: Wrap lines at 80 columns Fix the following warning detected by checkpatch.pl: WARNING: line over 80 characters TEST=Build and run on Galileo Gen2 Change-Id: I74f25da5c53bd518189ce86817d6e3385b29c3b4 Signed-off-by: Lee Leahy Reviewed-on: https://review.coreboot.org/18850 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth --- src/cpu/intel/fsp_model_406dx/bootblock.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) (limited to 'src/cpu/intel/fsp_model_406dx') diff --git a/src/cpu/intel/fsp_model_406dx/bootblock.c b/src/cpu/intel/fsp_model_406dx/bootblock.c index ee4cfac2de..a208ec9fbe 100644 --- a/src/cpu/intel/fsp_model_406dx/bootblock.c +++ b/src/cpu/intel/fsp_model_406dx/bootblock.c @@ -33,11 +33,13 @@ static void check_for_warm_reset(void) { /* - * Check if INIT# is asserted by port 0xCF9 and whether RCBA has been set. - * If either is true, then this is a warm reset so execute a Hard Reset + * Check if INIT# is asserted by port 0xCF9 and whether RCBA has been + * set. If either is true, then this is a warm reset so execute a + * Hard Reset */ if ((inb(0xcf9) == 0x04) || - (pci_io_read_config32(SOC_LPC_DEV, RCBA) & RCBA_ENABLE)) { + (pci_io_read_config32(SOC_LPC_DEV, RCBA) + & RCBA_ENABLE)) { outb(0x00, 0xcf9); outb(0x06, 0xcf9); } -- cgit v1.2.3