From 5f06d53bdb3621ff9e232d4f070f9ff4bbacfa4c Mon Sep 17 00:00:00 2001 From: David Guckian Date: Mon, 9 Nov 2015 16:19:18 +0000 Subject: intel/fsp_rangeley: Load BSP microcode in bootblock Load microcode to BSP in bootblock so later on the FSP TempRamInit call will return with success. The updated fsp1_0 driver calls TempRamInit API with dummy microcode, so FSP will not handle the microcode load. If BSP is not loaded with microcode before calling TempRamInit API, the call will fail with error No Valid Microcode Was Found. Change-Id: I9c55acaf3353a759bb0119f0a5402a704ffb2c4a Signed-off-by: David Guckian Reviewed-on: http://review.coreboot.org/12367 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin Reviewed-by: York Yang --- src/cpu/intel/fsp_model_406dx/Makefile.inc | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'src/cpu/intel/fsp_model_406dx/Makefile.inc') diff --git a/src/cpu/intel/fsp_model_406dx/Makefile.inc b/src/cpu/intel/fsp_model_406dx/Makefile.inc index 7e18f1ba1e..91c7d96aa4 100644 --- a/src/cpu/intel/fsp_model_406dx/Makefile.inc +++ b/src/cpu/intel/fsp_model_406dx/Makefile.inc @@ -18,6 +18,10 @@ subdirs-y += ../../x86/name ramstage-y += acpi.c +ifeq ($(CONFIG_HAVE_CPU_MICROCODE_FILE), y) +cpu_microcode_bins += $(call strip_quotes,$(CONFIG_CPU_MICROCODE_FILE)) +endif + CPPFLAGS_romstage += -I$(src)/cpu/intel/fsp_model_406dx # We don't have microcode for this CPU # Use CONFIG_CPU_MICROCODE_CBFS_EXTERNAL with a binary microcode file -- cgit v1.2.3