From c2c634a089fa990418c363e2ff2e5ff70bdd3580 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Tue, 19 Nov 2019 18:37:28 +0100 Subject: nb/sb/cpu: Drop Intel Rangeley support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Relocatable ramstage, postcar stage and C_ENVIRONMENT_BOOTBLOCK are now mandatory features, which this platform lacks. Change-Id: I41589118579988617677cf48af5401bc35b23e05 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/36980 Tested-by: build bot (Jenkins) Reviewed-by: HAOUAS Elyes Reviewed-by: Kyösti Mälkki Reviewed-by: Angel Pons Reviewed-by: David Hendricks --- src/cpu/intel/fsp_model_406dx/Kconfig | 63 ----------------------------------- 1 file changed, 63 deletions(-) delete mode 100644 src/cpu/intel/fsp_model_406dx/Kconfig (limited to 'src/cpu/intel/fsp_model_406dx/Kconfig') diff --git a/src/cpu/intel/fsp_model_406dx/Kconfig b/src/cpu/intel/fsp_model_406dx/Kconfig deleted file mode 100644 index 3e71469947..0000000000 --- a/src/cpu/intel/fsp_model_406dx/Kconfig +++ /dev/null @@ -1,63 +0,0 @@ -## -## This file is part of the coreboot project. -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -config CPU_INTEL_FSP_MODEL_406DX - bool - -if CPU_INTEL_FSP_MODEL_406DX - -config CPU_SPECIFIC_OPTIONS - def_bool y - select PLATFORM_USES_FSP1_0 - select ARCH_BOOTBLOCK_X86_32 - select ARCH_VERSTAGE_X86_32 - select ARCH_ROMSTAGE_X86_32 - select ARCH_RAMSTAGE_X86_32 - select SMP - select MMX - select SSE2 - select UDELAY_TSC - select SUPPORT_CPU_UCODE_IN_CBFS - select MICROCODE_BLOB_NOT_IN_BLOB_REPO - select PARALLEL_CPU_INIT - select TSC_SYNC_MFENCE - select TSC_MONOTONIC_TIMER - select CPU_INTEL_COMMON - select CPU_INTEL_COMMON_TIMEBASE - select NO_SMM - - # Microcode header files are delivered in FSP package - select USES_MICROCODE_HEADER_FILES if HAVE_FSP_BIN - -choice - prompt "Rangeley CPU Stepping" - default FSP_MODEL_406DX_B0 - -config FSP_MODEL_406DX_A1 - bool "A1" - -config FSP_MODEL_406DX_B0 - bool "B0" - -endchoice - -config BOOTBLOCK_CPU_INIT - string - default "cpu/intel/fsp_model_406dx/bootblock.c" - -#set up microcode for rangeley POSTGOLD4 release -config CPU_MICROCODE_HEADER_FILES - string - default "../intel/cpu/rangeley/microcode/microcode-m01406d000e.h ../intel/cpu/rangeley/microcode/microcode-m01406d8128.h" - -endif #CPU_INTEL_FSP_MODEL_406DX -- cgit v1.2.3