From f251a6d7d48d9ae91d4cce7195952395762e07a8 Mon Sep 17 00:00:00 2001 From: Alexander Couzens Date: Wed, 28 Jan 2015 01:51:04 +0100 Subject: cpu/intel: >= nehalem: add comments to msr finalize's Improve documentation of lock down MSRs in finalize(). Most of these aren't documented in public MSRs. Change-Id: I4fc47bb9b71bdd7907aae65fc18b419a17ae8547 Signed-off-by: Alexander Couzens Reviewed-on: http://review.coreboot.org/8294 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc Reviewed-by: Peter Stuge --- src/cpu/intel/fsp_model_206ax/finalize.c | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'src/cpu/intel/fsp_model_206ax') diff --git a/src/cpu/intel/fsp_model_206ax/finalize.c b/src/cpu/intel/fsp_model_206ax/finalize.c index 4ed5d1e5f8..534b1578c9 100644 --- a/src/cpu/intel/fsp_model_206ax/finalize.c +++ b/src/cpu/intel/fsp_model_206ax/finalize.c @@ -24,6 +24,11 @@ #include #include "model_206ax.h" +/* MSR Documentation based on + * "Sandy Bridge Processor Family BIOS Writer's Guide (BWG)" + * Document Number 504790 + * Revision 1.6.0, June 2012 */ + static void msr_set_bit(unsigned reg, unsigned bit) { msr_t msr = rdmsr(reg); @@ -43,6 +48,7 @@ static void msr_set_bit(unsigned reg, unsigned bit) void intel_model_206ax_finalize_smm(void) { + /* Lock C-State MSR */ msr_set_bit(MSR_PMG_CST_CONFIG_CONTROL, 15); /* Lock AES-NI only if supported */ @@ -67,6 +73,9 @@ void intel_model_206ax_finalize_smm(void) msr_set_bit(MSR_PP1_POWER_LIMIT, 31); #endif + /* Lock TM interupts - route thermal events to all processors */ msr_set_bit(MSR_MISC_PWR_MGMT, 22); + + /* Lock memory configuration to protect SMM */ msr_set_bit(MSR_LT_LOCK_MEMORY, 0); } -- cgit v1.2.3