From 158d00148f77569fc4a49176bcfeb4e0f990a1ff Mon Sep 17 00:00:00 2001
From: Martin Roth <martinroth@google.com>
Date: Mon, 26 Oct 2015 10:07:24 -0600
Subject: cpu/intel/fsp_model_206ax: Load microcode in coreboot

Intel's FSP 1.0 platforms are moving back to loading microcode in
coreboot instead of in the FSP.  Update the Ivy Bridge chips to
be compatible.

Change-Id: I4af155dea51e89ab9595b922c95ceade29a2dc52
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: http://review.coreboot.org/12196
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: York Yang <york.yang@intel.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
---
 src/cpu/intel/fsp_model_206ax/bootblock.c | 2 ++
 1 file changed, 2 insertions(+)

(limited to 'src/cpu/intel/fsp_model_206ax/bootblock.c')

diff --git a/src/cpu/intel/fsp_model_206ax/bootblock.c b/src/cpu/intel/fsp_model_206ax/bootblock.c
index 28cbd7ef77..5543347d53 100644
--- a/src/cpu/intel/fsp_model_206ax/bootblock.c
+++ b/src/cpu/intel/fsp_model_206ax/bootblock.c
@@ -24,8 +24,10 @@
 #include <cpu/x86/mtrr.h>
 #include <arch/io.h>
 
+#include <cpu/intel/microcode/microcode.c>
 #include "model_206ax.h"
 
 static void bootblock_cpu_init(void)
 {
+	intel_update_microcode_from_cbfs();
 }
-- 
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