From bdafcfa55509d0cf2cbbb686411f569d56d3916c Mon Sep 17 00:00:00 2001 From: Marc Jones Date: Tue, 29 Oct 2013 17:46:54 -0600 Subject: Add the Intel FSP 206ax CPU core support Add support for 206ax using the Intel FSP. The FSP is different enough to warrant its own source files for now. It has different CAR code, micorcode, and FSP inclusion. It may be possible to combine this code with the mrc based solution used by the chromebooks in the future. Change-Id: I5105631af34e9c3a804ace908c4205f073abb9b4 Signed-off-by: Marc Jones Reviewed-on: http://review.coreboot.org/4016 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich --- src/cpu/intel/fsp_model_206ax/Makefile.inc | 12 ++++++++++++ 1 file changed, 12 insertions(+) create mode 100644 src/cpu/intel/fsp_model_206ax/Makefile.inc (limited to 'src/cpu/intel/fsp_model_206ax/Makefile.inc') diff --git a/src/cpu/intel/fsp_model_206ax/Makefile.inc b/src/cpu/intel/fsp_model_206ax/Makefile.inc new file mode 100644 index 0000000000..1ea9c2aa49 --- /dev/null +++ b/src/cpu/intel/fsp_model_206ax/Makefile.inc @@ -0,0 +1,12 @@ +ramstage-y += model_206ax_init.c +subdirs-y += ../../x86/name + +ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += acpi.c + +smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c + +cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c + +cpu_incs += $(src)/cpu/intel/fsp_model_206ax/cache_as_ram.inc + +CC := $(CC) -I$(CONFIG_MICROCODE_INCLUDE_PATH) -- cgit v1.2.3