From 158d00148f77569fc4a49176bcfeb4e0f990a1ff Mon Sep 17 00:00:00 2001 From: Martin Roth Date: Mon, 26 Oct 2015 10:07:24 -0600 Subject: cpu/intel/fsp_model_206ax: Load microcode in coreboot Intel's FSP 1.0 platforms are moving back to loading microcode in coreboot instead of in the FSP. Update the Ivy Bridge chips to be compatible. Change-Id: I4af155dea51e89ab9595b922c95ceade29a2dc52 Signed-off-by: Martin Roth Reviewed-on: http://review.coreboot.org/12196 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: York Yang Reviewed-by: Patrick Georgi --- src/cpu/intel/fsp_model_206ax/Kconfig | 7 +------ 1 file changed, 1 insertion(+), 6 deletions(-) (limited to 'src/cpu/intel/fsp_model_206ax/Kconfig') diff --git a/src/cpu/intel/fsp_model_206ax/Kconfig b/src/cpu/intel/fsp_model_206ax/Kconfig index 606000e4be..a1b3d71a8f 100644 --- a/src/cpu/intel/fsp_model_206ax/Kconfig +++ b/src/cpu/intel/fsp_model_206ax/Kconfig @@ -37,7 +37,7 @@ config CPU_SPECIFIC_OPTIONS select SSE2 select UDELAY_LAPIC select SMM_TSEG - select SUPPORT_CPU_UCODE_IN_CBFS if HAVE_FSP_BIN + select SUPPORT_CPU_UCODE_IN_CBFS select PARALLEL_CPU_INIT select TSC_SYNC_MFENCE select LAPIC_MONOTONIC_TIMER @@ -54,9 +54,4 @@ config ENABLE_VMX bool "Enable VMX for virtualization" default n -config CPU_MICROCODE_CBFS_LOC - hex - depends on SUPPORT_CPU_UCODE_IN_CBFS - default 0xfff70000 - endif -- cgit v1.2.3