From 3165c46f451ccc2e223167aba84343cf8f269e35 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Thu, 18 Dec 2014 21:50:50 +0200 Subject: intel/truxton: Add dummy cache-as-ram region MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Board has no chance of working without a cache_as_ram.inc, but without a specified CAR region we also break builds. Change-Id: I98e9db38c5e0a7bf4a1b8d2f8a693cc8d0c773b9 Signed-off-by: Kyösti Mälkki Reviewed-on: http://review.coreboot.org/7863 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer --- src/cpu/intel/ep80579/Kconfig | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) (limited to 'src/cpu/intel/ep80579') diff --git a/src/cpu/intel/ep80579/Kconfig b/src/cpu/intel/ep80579/Kconfig index 530c48f0e8..ec584288bf 100644 --- a/src/cpu/intel/ep80579/Kconfig +++ b/src/cpu/intel/ep80579/Kconfig @@ -5,3 +5,19 @@ config CPU_INTEL_EP80579 select ARCH_RAMSTAGE_X86_32 select SSE select SUPPORT_CPU_UCODE_IN_CBFS + select BROKEN_CAR_MIGRATE + +if CPU_INTEL_EP80579 + +# These are just dummy values to keep build happy. +# This CPU does not have tested cache_as_ram.inc. + +config DCACHE_RAM_BASE + hex + default 0xffaf8000 + +config DCACHE_RAM_SIZE + hex + default 0x8000 + +endif -- cgit v1.2.3