From 062b92ef654a97648380a1a9a9fe34229ee76e31 Mon Sep 17 00:00:00 2001 From: Michael Niewöhner Date: Tue, 20 Oct 2020 14:27:09 +0200 Subject: cpu/intel/common: rework code previously moved to common cpu code MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Rework the code moved to common code in CB:46274. This involves simplification by using appropriate helpers for MSR and CPUID, using macros instead of plain values for MSRs and cpu features and adding documentation to the header. Change-Id: I7615fc26625c44931577216ea42f0a733b99e131 Signed-off-by: Michael Niewöhner Reviewed-on: https://review.coreboot.org/c/coreboot/+/46588 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber --- src/cpu/intel/common/common.h | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'src/cpu/intel/common/common.h') diff --git a/src/cpu/intel/common/common.h b/src/cpu/intel/common/common.h index dd8c2b8a27..fdacd1f74b 100644 --- a/src/cpu/intel/common/common.h +++ b/src/cpu/intel/common/common.h @@ -33,10 +33,16 @@ bool intel_ht_sibling(void); */ void set_aesni_lock(void); +/* Enable local CPU APIC TPR (Task Priority Register) updates */ void enable_lapic_tpr(void); +/* Enable DCA (Direct Cache Access) */ void configure_dca_cap(void); +/* + * Set EPB (Energy Performance Bias) + * Possible values are 0 (performance) to 15 (powersave). + */ void set_energy_perf_bias(u8 policy); #endif -- cgit v1.2.3