From aaced4a932dc68268cebace63df079673960c17b Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Wed, 28 Nov 2018 13:53:15 +0100 Subject: cpu/intel/common: Use a common acpi/cpu.asl file Change-Id: Ifa5a3a22771ff2e0efa14fb765603fd5e0440d59 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/29894 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie Reviewed-by: David Guckian --- src/cpu/intel/common/acpi/cpu.asl | 36 ++++++++++++++++++++++++++++++++++++ 1 file changed, 36 insertions(+) create mode 100644 src/cpu/intel/common/acpi/cpu.asl (limited to 'src/cpu/intel/common/acpi') diff --git a/src/cpu/intel/common/acpi/cpu.asl b/src/cpu/intel/common/acpi/cpu.asl new file mode 100644 index 0000000000..6fad17f74e --- /dev/null +++ b/src/cpu/intel/common/acpi/cpu.asl @@ -0,0 +1,36 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* These come from the dynamically created CPU SSDT */ +External (\_PR.CNOT, MethodObj) + +/* Notify OS to re-read CPU tables */ +Method (PNOT) +{ + \_PR.CNOT (0x81) +} + +/* Notify OS to re-read CPU _PPC limit */ +Method (PPCN) +{ + \_PR.CNOT (0x80) +} + +/* Notify OS to re-read Throttle Limit tables */ +Method (TNOT) +{ + \_PR.CNOT (0x82) +} -- cgit v1.2.3