From 7841a7f82416e6ad1d00610cca43a3fa9cc6b320 Mon Sep 17 00:00:00 2001 From: Kyösti Mälkki Date: Mon, 11 Feb 2019 11:33:36 +0200 Subject: cpu/intel/common: Add CPU_INTEL_COMMON_TIMEBASE MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit To add a common tsc_freq_mhz() implementation, we need to guard againts soc-specific duplicate definitions. Change-Id: I37a34651d9e7d823ad5689d30739294358a97e31 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/31341 Reviewed-by: Arthur Heymans Reviewed-by: David Guckian Tested-by: build bot (Jenkins) --- src/cpu/intel/common/Makefile.inc | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) (limited to 'src/cpu/intel/common/Makefile.inc') diff --git a/src/cpu/intel/common/Makefile.inc b/src/cpu/intel/common/Makefile.inc index 2fc6da908b..c38e81c380 100644 --- a/src/cpu/intel/common/Makefile.inc +++ b/src/cpu/intel/common/Makefile.inc @@ -1,5 +1,10 @@ ramstage-y += common_init.c -romstage-$(CONFIG_UDELAY_LAPIC) += fsb.c -ramstage-$(CONFIG_UDELAY_LAPIC) += fsb.c -postcar-$(CONFIG_UDELAY_LAPIC) += fsb.c + +ifeq ($(CONFIG_CPU_INTEL_COMMON_TIMEBASE),y) +bootblock-y += fsb.c +verstage-y += fsb.c +romstage-y += fsb.c +postcar-y += fsb.c +ramstage-y += fsb.c smm-y += fsb.c +endif -- cgit v1.2.3