From 8160a2f63db5a04a846b434701a88b449cc6f05f Mon Sep 17 00:00:00 2001 From: Kyösti Mälkki Date: Mon, 27 Jun 2016 13:24:11 +0300 Subject: intel post-car: Split legacy sockets MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Move old sockets to use romstage_legacy.c, these are ones using intel/car/cache_as_ram.inc. These will not be converted to RELOCATABLE_RAMSTAGE as boards are candidates for getting dropped from the tree anyways. Change-Id: I2616b4edee53446f1875711291e9dfed2911e2fb Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/17280 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/cpu/intel/car/romstage_legacy.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) create mode 100644 src/cpu/intel/car/romstage_legacy.c (limited to 'src/cpu/intel/car') diff --git a/src/cpu/intel/car/romstage_legacy.c b/src/cpu/intel/car/romstage_legacy.c new file mode 100644 index 0000000000..560cd7af2a --- /dev/null +++ b/src/cpu/intel/car/romstage_legacy.c @@ -0,0 +1,20 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include + +void * asmlinkage romstage_main(unsigned long bist) +{ + mainboard_romstage_entry(bist); + return (void*)CONFIG_RAMTOP; +} -- cgit v1.2.3