From 717b6e3151b6ea42aaa4b1ab2a708e143d098878 Mon Sep 17 00:00:00 2001 From: Kyösti Mälkki Date: Thu, 17 May 2018 14:16:03 +0300 Subject: aopen/dxplplusu intel/e7505: Move to EARLY_CBMEM_INIT MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit With implementation of LATE_CBMEM_INIT, top-of-low-memory TOLM was adjusted late in ramstage. We do not allow that with EARLY_CBMEM_INIT so the previous maximum of 1024 MiB of MMIO space is now used with statically set TOLM. Also remove support code for the obsolete LATE_CBMEM_INIT this northbridge used. Change-Id: Ib3094903d7614d2212fbe1870248962fbc92e412 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/26585 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber --- src/cpu/intel/car/romstage.c | 23 ----------------------- 1 file changed, 23 deletions(-) (limited to 'src/cpu/intel/car') diff --git a/src/cpu/intel/car/romstage.c b/src/cpu/intel/car/romstage.c index 03a94eebd1..37e39428e2 100644 --- a/src/cpu/intel/car/romstage.c +++ b/src/cpu/intel/car/romstage.c @@ -63,26 +63,3 @@ asmlinkage void romstage_after_car(void) /* Load the ramstage. */ run_ramstage(); } - -#if IS_ENABLED(CONFIG_LATE_CBMEM_INIT) -/* setup_stack_and_mtrrs() determines the stack to use after - * cache-as-ram is torn down as well as the MTRR settings to use. */ -void *setup_stack_and_mtrrs(void) -{ - struct postcar_frame pcf; - - postcar_frame_init_lowmem(&pcf); - - /* Cache the ROM as WP just below 4GiB. */ - postcar_frame_add_mtrr(&pcf, CACHE_ROM_BASE, CACHE_ROM_SIZE, - MTRR_TYPE_WRPROT); - - /* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */ - postcar_frame_add_mtrr(&pcf, 0, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK); - - /* Save the number of MTRRs to setup. Return the stack location - * pointing to the number of MTRRs. - */ - return postcar_commit_mtrrs(&pcf); -} -#endif /* CONFIG_LATE_CBMEM_INIT */ -- cgit v1.2.3