From 2765a893ca355caaf7d859e2bff5eb58630e2ddb Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Thu, 1 Sep 2016 19:44:56 +0200 Subject: src/cpu: Improve code formatting Change-Id: I17d5efe382da5301a9f5d595186d0fb7576725ca Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/16391 Tested-by: build bot (Jenkins) Reviewed-by: Andrew Wu Reviewed-by: Antonello Dettori --- src/cpu/intel/car/cache_as_ram_ht.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/cpu/intel/car') diff --git a/src/cpu/intel/car/cache_as_ram_ht.inc b/src/cpu/intel/car/cache_as_ram_ht.inc index 3e2b3e24ac..024133b864 100644 --- a/src/cpu/intel/car/cache_as_ram_ht.inc +++ b/src/cpu/intel/car/cache_as_ram_ht.inc @@ -200,7 +200,7 @@ ap_init: post_code(0x27) /* Do not disable cache (so BSP can enable it). */ - movl %cr0, %eax + movl %cr0, %eax andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax movl %eax, %cr0 -- cgit v1.2.3