From 107f72e674a3fbe2cadb24d98bba53f432bc2e0c Mon Sep 17 00:00:00 2001 From: Kyösti Mälkki Date: Mon, 6 Jan 2014 11:06:26 +0200 Subject: Re-declare CACHE_ROM_SIZE as aligned ROM_SIZE for MTRR MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This change allows Kconfig options ROM_SIZE and CBFS_SIZE to be set with values that are not power of 2. The region programmed as WB cacheable will include all of ROM_SIZE. Side-effects to consider: Memory region below flash may be tagged WRPROT cacheable. As an example, with ROM_SIZE of 12 MB, CACHE_ROM_SIZE would be 16 MB. Since this can overlap CAR, we add an explicit test and fail on compile should this happen. To work around this problem, one needs to use CACHE_ROM_SIZE_OVERRIDE in the mainboard Kconfig and define a smaller region for WB cache. With this change flash regions outside CBFS are also tagged WRPROT cacheable. This covers IFD and ME and sections ChromeOS may use. Change-Id: I5e577900ff7e91606bef6d80033caaed721ce4bf Signed-off-by: Kyösti Mälkki Reviewed-on: http://review.coreboot.org/4625 Tested-by: build bot (Jenkins) Reviewed-by: Vladimir Serbinenko --- src/cpu/intel/car/cache_as_ram_ht.inc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'src/cpu/intel/car') diff --git a/src/cpu/intel/car/cache_as_ram_ht.inc b/src/cpu/intel/car/cache_as_ram_ht.inc index fe1e29a5b3..fb653168b2 100644 --- a/src/cpu/intel/car/cache_as_ram_ht.inc +++ b/src/cpu/intel/car/cache_as_ram_ht.inc @@ -392,7 +392,7 @@ no_msr_11e: movl $(~(CONFIG_RAMTOP - 1) | MTRRphysMaskValid), %eax wrmsr -#if CONFIG_CACHE_ROM_SIZE +#if CACHE_ROM_SIZE /* Enable caching and Speculative Reads for Flash ROM device. */ movl $MTRRphysBase_MSR(1), %ecx movl $(CACHE_ROM_BASE | MTRR_TYPE_WRPROT), %eax @@ -400,7 +400,7 @@ no_msr_11e: wrmsr movl $MTRRphysMask_MSR(1), %ecx rdmsr - movl $(~(CONFIG_CACHE_ROM_SIZE - 1) | MTRRphysMaskValid), %eax + movl $(~(CACHE_ROM_SIZE - 1) | MTRRphysMaskValid), %eax wrmsr #endif -- cgit v1.2.3