From 61ba7fb2d9ecd2cfd64dda0618d544e4429fee8e Mon Sep 17 00:00:00 2001 From: Kyösti Mälkki Date: Sat, 13 Jun 2020 20:34:54 +0300 Subject: cpu/intel: Remove obsolete comment in CAR setup MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit A looong time ago when cache_as_ram.S was built into romstage, the stage was also linked twice. First at a fixed low address and then again relocated at the final execute-in-place address. Change-Id: Ic624feef6794f2c24e38459a45583d84fc07a484 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/42347 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber --- src/cpu/intel/car/p4-netburst/cache_as_ram.S | 4 ---- 1 file changed, 4 deletions(-) (limited to 'src/cpu/intel/car/p4-netburst') diff --git a/src/cpu/intel/car/p4-netburst/cache_as_ram.S b/src/cpu/intel/car/p4-netburst/cache_as_ram.S index 806102f0b0..4e36538414 100644 --- a/src/cpu/intel/car/p4-netburst/cache_as_ram.S +++ b/src/cpu/intel/car/p4-netburst/cache_as_ram.S @@ -322,10 +322,6 @@ cache_rom: /* Enable cache for our code in Flash because we do XIP here */ movl $MTRR_PHYS_BASE(1), %ecx xorl %edx, %edx - /* - * IMPORTANT: The following calculation _must_ be done at runtime. See - * https://mail.coreboot.org/pipermail/coreboot/2010-October/060922.html - */ movl $_program, %eax andl $_xip_mtrr_mask, %eax orl $MTRR_TYPE_WRPROT, %eax -- cgit v1.2.3