From b8c2aa2ce8fb74bd8bf3407e0a20240c7f41eadf Mon Sep 17 00:00:00 2001 From: Myles Watson Date: Thu, 7 Feb 2008 20:37:37 +0000 Subject: Change references to qemu in Coreboot-v2 calls to qemu-x86. The patch was followed by these svn commands: svn mv targets/emulation/qemu-i386/ targets/emulation/qemu-x86 svn mv --force targets/emulation/qemu-i386/ targets/emulation/qemu-x86 svn mv --force src/mainboard/emulation/qemu-i386/ src/mainboard/emulation/qemu-x86 svn mv --force src/cpu/emulation/qemu-i386/ src/cpu/emulation/qemu-x86 Signed-off-by: Myles Watson Acked-by: Stefan Reinauer git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3093 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1 --- src/cpu/emulation/qemu-i386/Config.lb | 2 - src/cpu/emulation/qemu-i386/chip.h | 6 -- src/cpu/emulation/qemu-i386/northbridge.c | 153 ------------------------------ src/cpu/emulation/qemu-i386/northbridge.h | 5 - src/cpu/emulation/qemu-x86/Config.lb | 2 + src/cpu/emulation/qemu-x86/chip.h | 6 ++ src/cpu/emulation/qemu-x86/northbridge.c | 153 ++++++++++++++++++++++++++++++ src/cpu/emulation/qemu-x86/northbridge.h | 5 + 8 files changed, 166 insertions(+), 166 deletions(-) delete mode 100644 src/cpu/emulation/qemu-i386/Config.lb delete mode 100644 src/cpu/emulation/qemu-i386/chip.h delete mode 100644 src/cpu/emulation/qemu-i386/northbridge.c delete mode 100644 src/cpu/emulation/qemu-i386/northbridge.h create mode 100644 src/cpu/emulation/qemu-x86/Config.lb create mode 100644 src/cpu/emulation/qemu-x86/chip.h create mode 100644 src/cpu/emulation/qemu-x86/northbridge.c create mode 100644 src/cpu/emulation/qemu-x86/northbridge.h (limited to 'src/cpu/emulation') diff --git a/src/cpu/emulation/qemu-i386/Config.lb b/src/cpu/emulation/qemu-i386/Config.lb deleted file mode 100644 index 4a0c2c8658..0000000000 --- a/src/cpu/emulation/qemu-i386/Config.lb +++ /dev/null @@ -1,2 +0,0 @@ -config chip.h -object northbridge.o diff --git a/src/cpu/emulation/qemu-i386/chip.h b/src/cpu/emulation/qemu-i386/chip.h deleted file mode 100644 index 6ade17bb01..0000000000 --- a/src/cpu/emulation/qemu-i386/chip.h +++ /dev/null @@ -1,6 +0,0 @@ -struct cpu_emulation_qemu_i386_config -{ -}; - -extern struct chip_operations cpu_emulation_qemu_i386_ops; - diff --git a/src/cpu/emulation/qemu-i386/northbridge.c b/src/cpu/emulation/qemu-i386/northbridge.c deleted file mode 100644 index 505511ac95..0000000000 --- a/src/cpu/emulation/qemu-i386/northbridge.c +++ /dev/null @@ -1,153 +0,0 @@ -#include -#include -#include -#include -#include -#include -#include -#include -#include "chip.h" -#include "northbridge.h" - -#define BRIDGE_IO_MASK (IORESOURCE_IO | IORESOURCE_MEM) - -static void pci_domain_read_resources(device_t dev) -{ - struct resource *resource; - - /* Initialize the system wide io space constraints */ - resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0,0)); - resource->limit = 0xffffUL; - resource->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; - - /* Initialize the system wide memory resources constraints */ - resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1,0)); - resource->limit = 0xffffffffULL; - resource->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; -} - -static void ram_resource(device_t dev, unsigned long index, - unsigned long basek, unsigned long sizek) -{ - struct resource *resource; - - if (!sizek) { - return; - } - resource = new_resource(dev, index); - resource->base = ((resource_t)basek) << 10; - resource->size = ((resource_t)sizek) << 10; - resource->flags = IORESOURCE_MEM | IORESOURCE_CACHEABLE | \ - IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; -} - -static void tolm_test(void *gp, struct device *dev, struct resource *new) -{ - struct resource **best_p = gp; - struct resource *best; - best = *best_p; - if (!best || (best->base > new->base)) { - best = new; - } - *best_p = best; -} - -static uint32_t find_pci_tolm(struct bus *bus) -{ - struct resource *min; - uint32_t tolm; - min = 0; - search_bus_resources(bus, IORESOURCE_MEM, IORESOURCE_MEM, tolm_test, &min); - tolm = 0xffffffffUL; - if (min && tolm > min->base) { - tolm = min->base; - } - return tolm; -} - -static void pci_domain_set_resources(device_t dev) -{ - static const uint8_t ramregs[] = { - 0x5a, 0x5b, 0x5c, 0x5d, 0x5e, 0x5f, 0x56, 0x57 - }; - device_t mc_dev; - uint32_t pci_tolm; - - pci_tolm = find_pci_tolm(&dev->link[0]); - mc_dev = dev->link[0].children; - if (mc_dev) { - unsigned long tomk, tolmk; - unsigned char rambits; - int i, idx; - - for(rambits = 0, i = 0; i < sizeof(ramregs)/sizeof(ramregs[0]); i++) { - unsigned char reg; - reg = pci_read_config8(mc_dev, ramregs[i]); - /* these are ENDING addresses, not sizes. - * if there is memory in this slot, then reg will be > rambits. - * So we just take the max, that gives us total. - * We take the highest one to cover for once and future coreboot - * bugs. We warn about bugs. - */ - if (reg > rambits) - rambits = reg; - if (reg < rambits) - printk_err("ERROR! register 0x%x is not set!\n", - ramregs[i]); - } - if (rambits == 0) { - printk_err("RAM size config registers are empty; defaulting to 64 MBytes\n"); - rambits = 8; - } - printk_debug("I would set ram size to 0x%x Kbytes\n", (rambits)*8*1024); - tomk = rambits*8*1024; - /* Compute the top of Low memory */ - tolmk = pci_tolm >> 10; - if (tolmk >= tomk) { - /* The PCI hole does not overlap memory. - */ - tolmk = tomk; - } - /* Report the memory regions */ - idx = 10; - ram_resource(dev, idx++, 0, tolmk); - } - assign_resources(&dev->link[0]); -} - -static unsigned int pci_domain_scan_bus(device_t dev, unsigned int max) -{ - max = pci_scan_bus(&dev->link[0], PCI_DEVFN(0, 0), 0xff, max); - return max; -} - -static struct device_operations pci_domain_ops = { - .read_resources = pci_domain_read_resources, - .set_resources = pci_domain_set_resources, - .enable_resources = enable_childrens_resources, - .init = 0, - .scan_bus = pci_domain_scan_bus, -}; - -static void enable_dev(struct device *dev) -{ - /* Set the operations if it is a special bus type */ - if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) { - dev->ops = &pci_domain_ops; - pci_set_method(dev); - } -} - -struct chip_operations cpu_emulation_qemu_i386_ops = { - CHIP_NAME("QEMU Northbridge") - .enable_dev = enable_dev, -}; - -void udelay(int usecs) -{ - int i; - for(i = 0; i < usecs; i++) - outb(i&0xff, 0x80); -} - - diff --git a/src/cpu/emulation/qemu-i386/northbridge.h b/src/cpu/emulation/qemu-i386/northbridge.h deleted file mode 100644 index c74e63b97d..0000000000 --- a/src/cpu/emulation/qemu-i386/northbridge.h +++ /dev/null @@ -1,5 +0,0 @@ -#ifndef NORTHBRIDGE_EMULATION_QEMU_I386_H -#define NORTHBRIDGE_EMULATION_QEMU_I386_H - - -#endif /* NORTHBRIDGE_EMULATION_QEMU_I386 */ diff --git a/src/cpu/emulation/qemu-x86/Config.lb b/src/cpu/emulation/qemu-x86/Config.lb new file mode 100644 index 0000000000..4a0c2c8658 --- /dev/null +++ b/src/cpu/emulation/qemu-x86/Config.lb @@ -0,0 +1,2 @@ +config chip.h +object northbridge.o diff --git a/src/cpu/emulation/qemu-x86/chip.h b/src/cpu/emulation/qemu-x86/chip.h new file mode 100644 index 0000000000..1183200ff7 --- /dev/null +++ b/src/cpu/emulation/qemu-x86/chip.h @@ -0,0 +1,6 @@ +struct cpu_emulation_qemu_x86_config +{ +}; + +extern struct chip_operations cpu_emulation_qemu_x86_ops; + diff --git a/src/cpu/emulation/qemu-x86/northbridge.c b/src/cpu/emulation/qemu-x86/northbridge.c new file mode 100644 index 0000000000..694df64ec6 --- /dev/null +++ b/src/cpu/emulation/qemu-x86/northbridge.c @@ -0,0 +1,153 @@ +#include +#include +#include +#include +#include +#include +#include +#include +#include "chip.h" +#include "northbridge.h" + +#define BRIDGE_IO_MASK (IORESOURCE_IO | IORESOURCE_MEM) + +static void pci_domain_read_resources(device_t dev) +{ + struct resource *resource; + + /* Initialize the system wide io space constraints */ + resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0,0)); + resource->limit = 0xffffUL; + resource->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; + + /* Initialize the system wide memory resources constraints */ + resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1,0)); + resource->limit = 0xffffffffULL; + resource->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; +} + +static void ram_resource(device_t dev, unsigned long index, + unsigned long basek, unsigned long sizek) +{ + struct resource *resource; + + if (!sizek) { + return; + } + resource = new_resource(dev, index); + resource->base = ((resource_t)basek) << 10; + resource->size = ((resource_t)sizek) << 10; + resource->flags = IORESOURCE_MEM | IORESOURCE_CACHEABLE | \ + IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; +} + +static void tolm_test(void *gp, struct device *dev, struct resource *new) +{ + struct resource **best_p = gp; + struct resource *best; + best = *best_p; + if (!best || (best->base > new->base)) { + best = new; + } + *best_p = best; +} + +static uint32_t find_pci_tolm(struct bus *bus) +{ + struct resource *min; + uint32_t tolm; + min = 0; + search_bus_resources(bus, IORESOURCE_MEM, IORESOURCE_MEM, tolm_test, &min); + tolm = 0xffffffffUL; + if (min && tolm > min->base) { + tolm = min->base; + } + return tolm; +} + +static void pci_domain_set_resources(device_t dev) +{ + static const uint8_t ramregs[] = { + 0x5a, 0x5b, 0x5c, 0x5d, 0x5e, 0x5f, 0x56, 0x57 + }; + device_t mc_dev; + uint32_t pci_tolm; + + pci_tolm = find_pci_tolm(&dev->link[0]); + mc_dev = dev->link[0].children; + if (mc_dev) { + unsigned long tomk, tolmk; + unsigned char rambits; + int i, idx; + + for(rambits = 0, i = 0; i < sizeof(ramregs)/sizeof(ramregs[0]); i++) { + unsigned char reg; + reg = pci_read_config8(mc_dev, ramregs[i]); + /* these are ENDING addresses, not sizes. + * if there is memory in this slot, then reg will be > rambits. + * So we just take the max, that gives us total. + * We take the highest one to cover for once and future coreboot + * bugs. We warn about bugs. + */ + if (reg > rambits) + rambits = reg; + if (reg < rambits) + printk_err("ERROR! register 0x%x is not set!\n", + ramregs[i]); + } + if (rambits == 0) { + printk_err("RAM size config registers are empty; defaulting to 64 MBytes\n"); + rambits = 8; + } + printk_debug("I would set ram size to 0x%x Kbytes\n", (rambits)*8*1024); + tomk = rambits*8*1024; + /* Compute the top of Low memory */ + tolmk = pci_tolm >> 10; + if (tolmk >= tomk) { + /* The PCI hole does not overlap memory. + */ + tolmk = tomk; + } + /* Report the memory regions */ + idx = 10; + ram_resource(dev, idx++, 0, tolmk); + } + assign_resources(&dev->link[0]); +} + +static unsigned int pci_domain_scan_bus(device_t dev, unsigned int max) +{ + max = pci_scan_bus(&dev->link[0], PCI_DEVFN(0, 0), 0xff, max); + return max; +} + +static struct device_operations pci_domain_ops = { + .read_resources = pci_domain_read_resources, + .set_resources = pci_domain_set_resources, + .enable_resources = enable_childrens_resources, + .init = 0, + .scan_bus = pci_domain_scan_bus, +}; + +static void enable_dev(struct device *dev) +{ + /* Set the operations if it is a special bus type */ + if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) { + dev->ops = &pci_domain_ops; + pci_set_method(dev); + } +} + +struct chip_operations cpu_emulation_qemu_x86_ops = { + CHIP_NAME("QEMU Northbridge") + .enable_dev = enable_dev, +}; + +void udelay(int usecs) +{ + int i; + for(i = 0; i < usecs; i++) + outb(i&0xff, 0x80); +} + + diff --git a/src/cpu/emulation/qemu-x86/northbridge.h b/src/cpu/emulation/qemu-x86/northbridge.h new file mode 100644 index 0000000000..9ff688be2f --- /dev/null +++ b/src/cpu/emulation/qemu-x86/northbridge.h @@ -0,0 +1,5 @@ +#ifndef NORTHBRIDGE_EMULATION_QEMU_X86_H +#define NORTHBRIDGE_EMULATION_QEMU_X86_H + + +#endif /* NORTHBRIDGE_EMULATION_QEMU_X86 */ -- cgit v1.2.3