From 8a13743569a8d1ac61b8a52d2dab621ff4041de2 Mon Sep 17 00:00:00 2001 From: Alexandru Gagniuc Date: Mon, 5 Oct 2015 08:00:51 -0700 Subject: x86 chipsets: Link non-code flow CHIPSET_BOOTBLOCK_INCLUDE files Non-code flow assembly stubs do not have to be included in bootblock.S, now that we have more freedom in bootblock linking. Rather than bringing these stubs to the config system, just link them in the bootblock. Note that we cannot fully remove CHIPSET_BOOTBLOCK_INCLUDE at this point, as some intel SOCs use this stub for code flow. objdump -h build/cbfs/fallback/bootblock.debug on a few random boards confirms that the appropriate sections are still included in the final binary. Change-Id: Id3f9ece14e399c1cc83090f407780c4a05a076f0 Signed-off-by: Alexandru Gagniuc Reviewed-on: https://review.coreboot.org/11856 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth --- src/cpu/dmp/vortex86ex/Kconfig | 4 - src/cpu/dmp/vortex86ex/Makefile.inc | 2 + src/cpu/dmp/vortex86ex/biosdata.S | 80 +++++++++++++ src/cpu/dmp/vortex86ex/biosdata.inc | 80 ------------- src/cpu/dmp/vortex86ex/biosdata_ex.S | 172 +++++++++++++++++++++++++++ src/cpu/dmp/vortex86ex/biosdata_ex.inc | 172 --------------------------- src/cpu/dmp/vortex86ex/chipset_bootblock.inc | 2 - 7 files changed, 254 insertions(+), 258 deletions(-) create mode 100644 src/cpu/dmp/vortex86ex/biosdata.S delete mode 100644 src/cpu/dmp/vortex86ex/biosdata.inc create mode 100644 src/cpu/dmp/vortex86ex/biosdata_ex.S delete mode 100644 src/cpu/dmp/vortex86ex/biosdata_ex.inc delete mode 100644 src/cpu/dmp/vortex86ex/chipset_bootblock.inc (limited to 'src/cpu/dmp') diff --git a/src/cpu/dmp/vortex86ex/Kconfig b/src/cpu/dmp/vortex86ex/Kconfig index 1f43f769b2..1af7ec4bf8 100644 --- a/src/cpu/dmp/vortex86ex/Kconfig +++ b/src/cpu/dmp/vortex86ex/Kconfig @@ -73,8 +73,4 @@ config PLL_500_375_33 endchoice -config CHIPSET_BOOTBLOCK_INCLUDE - string - default "cpu/dmp/vortex86ex/chipset_bootblock.inc" - endif diff --git a/src/cpu/dmp/vortex86ex/Makefile.inc b/src/cpu/dmp/vortex86ex/Makefile.inc index 76df34caae..6b4d0ba74e 100644 --- a/src/cpu/dmp/vortex86ex/Makefile.inc +++ b/src/cpu/dmp/vortex86ex/Makefile.inc @@ -21,5 +21,7 @@ subdirs-y += ../../x86/smm bootblock-y += biosdata.ld bootblock-y += biosdata_ex.ld +bootblock-y += biosdata.S +bootblock-y += biosdata_ex.S ROMCCFLAGS := -mcpu=i386 -O2 diff --git a/src/cpu/dmp/vortex86ex/biosdata.S b/src/cpu/dmp/vortex86ex/biosdata.S new file mode 100644 index 0000000000..c08242adba --- /dev/null +++ b/src/cpu/dmp/vortex86ex/biosdata.S @@ -0,0 +1,80 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 DMP Electronics Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + .section ".dmp_reserved", "a", @progbits + + .skip 0x3c000 - 0x3bc00, 0xff + +.previous + + .section ".dmp_kbd_fw_part2", "a", @progbits + + .skip 0x3d000 - 0x3c000, 0xff + +.previous + + .section ".dmp_mtbf_low_cnt", "a", @progbits + + .skip 0x3e000 - 0x3d000, 0xff + +.previous + + .section ".dmp_kbd_fw_part1", "a", @progbits + + #include "dmp_kbd_fw_part1.inc" + +.previous + + .section ".dmp_spi_flash_disk_driver", "a", @progbits + + .skip 0x3f800 - 0x3f000, 0xff + +.previous + + .section ".dmp_frontdoor", "a", @progbits + + .skip 0x3fd00 - 0x3f800, 0xff + +.previous + + .section ".dmp_isoinfo", "a", @progbits + + .skip 26 * 16, 0xff + +.previous + + .section ".dmp_isodata_checksum", "a", @progbits + + .skip 8, 0xff + +.previous + + .section ".dmp_mac", "a", @progbits + + .skip 6, 0xff + +.previous + + .section ".dmp_mtbf_limit", "a", @progbits + + .skip 3, 0xff + +.previous + + .section ".dmp_isodata", "a", @progbits + + .skip 32, 0xff + +.previous diff --git a/src/cpu/dmp/vortex86ex/biosdata.inc b/src/cpu/dmp/vortex86ex/biosdata.inc deleted file mode 100644 index c08242adba..0000000000 --- a/src/cpu/dmp/vortex86ex/biosdata.inc +++ /dev/null @@ -1,80 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 DMP Electronics Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - - .section ".dmp_reserved", "a", @progbits - - .skip 0x3c000 - 0x3bc00, 0xff - -.previous - - .section ".dmp_kbd_fw_part2", "a", @progbits - - .skip 0x3d000 - 0x3c000, 0xff - -.previous - - .section ".dmp_mtbf_low_cnt", "a", @progbits - - .skip 0x3e000 - 0x3d000, 0xff - -.previous - - .section ".dmp_kbd_fw_part1", "a", @progbits - - #include "dmp_kbd_fw_part1.inc" - -.previous - - .section ".dmp_spi_flash_disk_driver", "a", @progbits - - .skip 0x3f800 - 0x3f000, 0xff - -.previous - - .section ".dmp_frontdoor", "a", @progbits - - .skip 0x3fd00 - 0x3f800, 0xff - -.previous - - .section ".dmp_isoinfo", "a", @progbits - - .skip 26 * 16, 0xff - -.previous - - .section ".dmp_isodata_checksum", "a", @progbits - - .skip 8, 0xff - -.previous - - .section ".dmp_mac", "a", @progbits - - .skip 6, 0xff - -.previous - - .section ".dmp_mtbf_limit", "a", @progbits - - .skip 3, 0xff - -.previous - - .section ".dmp_isodata", "a", @progbits - - .skip 32, 0xff - -.previous diff --git a/src/cpu/dmp/vortex86ex/biosdata_ex.S b/src/cpu/dmp/vortex86ex/biosdata_ex.S new file mode 100644 index 0000000000..5ed17c67d1 --- /dev/null +++ b/src/cpu/dmp/vortex86ex/biosdata_ex.S @@ -0,0 +1,172 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 DMP Electronics Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "config.h" + +/* +PLL Freq = 25 * NS /(MS * 2^RS) +CPU Freq = PLL/(CPU_DIV+2) +DRAM Freq = PLL/2(DRAM_DIV+1) + +DDR3 +CPU/DRAM/PCI B6 B7 BB BC BD BF +200/200/33 30 03 0F 02 8F 07 +300/300/33 48 03 0F 02 1F 07 +300/300/33 48 03 0F 3A DF 07 ; write leveling disable, cpu bypass disable +300/300/33 48 03 0F 22 3F 07 ; cpu bypass disable +300/300/100 48 03 23 02 7F 07 +400/200/33 60 43 0F 02 3F 07 ; without 200MHz timing, so set 300MHz timing +400/200/100 60 43 23 02 4F 07 +400/400/33 60 03 0F 02 BF 09 +500/250/33 50 42 0F 02 DF 07 +500/500/33 78 03 0F 02 4F 09 +400/300/33 90 53 0F 02 3F 07 +400/300/33 90 53 0F 1A DF 07 ; write leveling/gate training disable +400/300/100 90 53 23 02 9F 07 +444/333/33 A0 53 0F 02 5F 08 +466/350/33 A8 53 0F 02 DF 09 +500/375/33 B4 53 0F 02 AF 09 +*/ + +#if CONFIG_PLL_200_200_33 + // 200/200/33 30 03 0F 02 8F 07 + byte_fffb6 = 0x30 + byte_fffb7 = 0x03 + byte_fffbb = 0x0f + byte_fffbc = 0x02 + byte_fffbe = 0xff + byte_fffbf = 0x07 +#elif CONFIG_PLL_300_300_33 + // 300/300/33 48 03 0F 02 1F 07 + byte_fffb6 = 0x48 + byte_fffb7 = 0x03 + byte_fffbb = 0x0f + byte_fffbc = 0x02 + byte_fffbe = 0xff + byte_fffbf = 0x07 +#elif CONFIG_PLL_300_300_100 + // 300/300/100 48 03 23 02 7F 07 + byte_fffb6 = 0x48 + byte_fffb7 = 0x03 + byte_fffbb = 0x23 + byte_fffbc = 0x02 + byte_fffbe = 0xff + byte_fffbf = 0x07 +#elif CONFIG_PLL_400_200_33 + // 400/200/33 60 43 0F 02 3F 07 ; without 200MHz timing, so set 300MHz timing + byte_fffb6 = 0x60 + byte_fffb7 = 0x43 + byte_fffbb = 0x0f + byte_fffbc = 0x02 + byte_fffbe = 0xff + byte_fffbf = 0x07 +#elif CONFIG_PLL_400_200_100 + // 400/200/100 60 43 23 02 4F 07 + byte_fffb6 = 0x60 + byte_fffb7 = 0x43 + byte_fffbb = 0x23 + byte_fffbc = 0x02 + byte_fffbe = 0xff + byte_fffbf = 0x07 +#elif CONFIG_PLL_400_400_33 + // 400/400/33 60 03 0F 02 BF 09 + byte_fffb6 = 0x60 + byte_fffb7 = 0x03 + byte_fffbb = 0x0f + byte_fffbc = 0x02 + byte_fffbe = 0xff + byte_fffbf = 0x09 +#elif CONFIG_PLL_500_250_33 + // 500/250/33 50 42 0F 02 DF 07 + byte_fffb6 = 0x50 + byte_fffb7 = 0x42 + byte_fffbb = 0x0f + byte_fffbc = 0x02 + byte_fffbe = 0xff + byte_fffbf = 0x07 +#elif CONFIG_PLL_500_500_33 + // 500/500/33 78 03 0F 02 4F 09 + byte_fffb6 = 0x78 + byte_fffb7 = 0x03 + byte_fffbb = 0x0f + byte_fffbc = 0x02 + byte_fffbe = 0xff + byte_fffbf = 0x09 +#elif CONFIG_PLL_400_300_33 + // 400/300/33 90 53 0F 02 3F 07 + byte_fffb6 = 0x90 + byte_fffb7 = 0x53 + byte_fffbb = 0x0f + byte_fffbc = 0x02 + byte_fffbe = 0xff + byte_fffbf = 0x07 +#elif CONFIG_PLL_400_300_100 + // 400/300/100 90 53 23 02 9F 07 + byte_fffb6 = 0x90 + byte_fffb7 = 0x53 + byte_fffbb = 0x23 + byte_fffbc = 0x02 + byte_fffbe = 0xff + byte_fffbf = 0x07 +#elif CONFIG_PLL_444_333_33 + // 444/333/33 A0 53 0F 02 5F 08 + byte_fffb6 = 0xa0 + byte_fffb7 = 0x53 + byte_fffbb = 0x0f + byte_fffbc = 0x02 + byte_fffbe = 0xff + byte_fffbf = 0x08 +#elif CONFIG_PLL_466_350_33 + // 466/350/33 A8 53 0F 02 DF 09 + byte_fffb6 = 0xa8 + byte_fffb7 = 0x53 + byte_fffbb = 0x0f + byte_fffbc = 0x02 + byte_fffbe = 0xff + byte_fffbf = 0x09 +#elif CONFIG_PLL_500_375_33 + // 500/375/33 B4 53 0F 02 AF 09 + byte_fffb6 = 0xb4 + byte_fffb7 = 0x53 + byte_fffbb = 0x0f + byte_fffbc = 0x02 + byte_fffbe = 0xff + byte_fffbf = 0x09 +#else + #error Error Strap PLL config. +#endif + +tmp_sum = byte_fffb6 + byte_fffb7 + byte_fffbb + byte_fffbc +pll_checksum = ((tmp_sum >> 8) & 0x3) + ((tmp_sum >> 4) & 0x0f) + (tmp_sum & 0x0f) + +byte_fffbd = ((pll_checksum & 0x0f) << 4) | 0x0f + + .section ".a9123_crossbar_config", "a", @progbits + + .skip 0x3fdf0 - 0x3fd00, 0xff + +.previous + + .section ".a9123_strap_1", "a", @progbits + + .byte byte_fffb6, byte_fffb7 + +.previous + + .section ".a9123_strap_2", "a", @progbits + + .byte byte_fffbb, byte_fffbc, byte_fffbd, byte_fffbe, byte_fffbf + +.previous diff --git a/src/cpu/dmp/vortex86ex/biosdata_ex.inc b/src/cpu/dmp/vortex86ex/biosdata_ex.inc deleted file mode 100644 index 5ed17c67d1..0000000000 --- a/src/cpu/dmp/vortex86ex/biosdata_ex.inc +++ /dev/null @@ -1,172 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 DMP Electronics Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include "config.h" - -/* -PLL Freq = 25 * NS /(MS * 2^RS) -CPU Freq = PLL/(CPU_DIV+2) -DRAM Freq = PLL/2(DRAM_DIV+1) - -DDR3 -CPU/DRAM/PCI B6 B7 BB BC BD BF -200/200/33 30 03 0F 02 8F 07 -300/300/33 48 03 0F 02 1F 07 -300/300/33 48 03 0F 3A DF 07 ; write leveling disable, cpu bypass disable -300/300/33 48 03 0F 22 3F 07 ; cpu bypass disable -300/300/100 48 03 23 02 7F 07 -400/200/33 60 43 0F 02 3F 07 ; without 200MHz timing, so set 300MHz timing -400/200/100 60 43 23 02 4F 07 -400/400/33 60 03 0F 02 BF 09 -500/250/33 50 42 0F 02 DF 07 -500/500/33 78 03 0F 02 4F 09 -400/300/33 90 53 0F 02 3F 07 -400/300/33 90 53 0F 1A DF 07 ; write leveling/gate training disable -400/300/100 90 53 23 02 9F 07 -444/333/33 A0 53 0F 02 5F 08 -466/350/33 A8 53 0F 02 DF 09 -500/375/33 B4 53 0F 02 AF 09 -*/ - -#if CONFIG_PLL_200_200_33 - // 200/200/33 30 03 0F 02 8F 07 - byte_fffb6 = 0x30 - byte_fffb7 = 0x03 - byte_fffbb = 0x0f - byte_fffbc = 0x02 - byte_fffbe = 0xff - byte_fffbf = 0x07 -#elif CONFIG_PLL_300_300_33 - // 300/300/33 48 03 0F 02 1F 07 - byte_fffb6 = 0x48 - byte_fffb7 = 0x03 - byte_fffbb = 0x0f - byte_fffbc = 0x02 - byte_fffbe = 0xff - byte_fffbf = 0x07 -#elif CONFIG_PLL_300_300_100 - // 300/300/100 48 03 23 02 7F 07 - byte_fffb6 = 0x48 - byte_fffb7 = 0x03 - byte_fffbb = 0x23 - byte_fffbc = 0x02 - byte_fffbe = 0xff - byte_fffbf = 0x07 -#elif CONFIG_PLL_400_200_33 - // 400/200/33 60 43 0F 02 3F 07 ; without 200MHz timing, so set 300MHz timing - byte_fffb6 = 0x60 - byte_fffb7 = 0x43 - byte_fffbb = 0x0f - byte_fffbc = 0x02 - byte_fffbe = 0xff - byte_fffbf = 0x07 -#elif CONFIG_PLL_400_200_100 - // 400/200/100 60 43 23 02 4F 07 - byte_fffb6 = 0x60 - byte_fffb7 = 0x43 - byte_fffbb = 0x23 - byte_fffbc = 0x02 - byte_fffbe = 0xff - byte_fffbf = 0x07 -#elif CONFIG_PLL_400_400_33 - // 400/400/33 60 03 0F 02 BF 09 - byte_fffb6 = 0x60 - byte_fffb7 = 0x03 - byte_fffbb = 0x0f - byte_fffbc = 0x02 - byte_fffbe = 0xff - byte_fffbf = 0x09 -#elif CONFIG_PLL_500_250_33 - // 500/250/33 50 42 0F 02 DF 07 - byte_fffb6 = 0x50 - byte_fffb7 = 0x42 - byte_fffbb = 0x0f - byte_fffbc = 0x02 - byte_fffbe = 0xff - byte_fffbf = 0x07 -#elif CONFIG_PLL_500_500_33 - // 500/500/33 78 03 0F 02 4F 09 - byte_fffb6 = 0x78 - byte_fffb7 = 0x03 - byte_fffbb = 0x0f - byte_fffbc = 0x02 - byte_fffbe = 0xff - byte_fffbf = 0x09 -#elif CONFIG_PLL_400_300_33 - // 400/300/33 90 53 0F 02 3F 07 - byte_fffb6 = 0x90 - byte_fffb7 = 0x53 - byte_fffbb = 0x0f - byte_fffbc = 0x02 - byte_fffbe = 0xff - byte_fffbf = 0x07 -#elif CONFIG_PLL_400_300_100 - // 400/300/100 90 53 23 02 9F 07 - byte_fffb6 = 0x90 - byte_fffb7 = 0x53 - byte_fffbb = 0x23 - byte_fffbc = 0x02 - byte_fffbe = 0xff - byte_fffbf = 0x07 -#elif CONFIG_PLL_444_333_33 - // 444/333/33 A0 53 0F 02 5F 08 - byte_fffb6 = 0xa0 - byte_fffb7 = 0x53 - byte_fffbb = 0x0f - byte_fffbc = 0x02 - byte_fffbe = 0xff - byte_fffbf = 0x08 -#elif CONFIG_PLL_466_350_33 - // 466/350/33 A8 53 0F 02 DF 09 - byte_fffb6 = 0xa8 - byte_fffb7 = 0x53 - byte_fffbb = 0x0f - byte_fffbc = 0x02 - byte_fffbe = 0xff - byte_fffbf = 0x09 -#elif CONFIG_PLL_500_375_33 - // 500/375/33 B4 53 0F 02 AF 09 - byte_fffb6 = 0xb4 - byte_fffb7 = 0x53 - byte_fffbb = 0x0f - byte_fffbc = 0x02 - byte_fffbe = 0xff - byte_fffbf = 0x09 -#else - #error Error Strap PLL config. -#endif - -tmp_sum = byte_fffb6 + byte_fffb7 + byte_fffbb + byte_fffbc -pll_checksum = ((tmp_sum >> 8) & 0x3) + ((tmp_sum >> 4) & 0x0f) + (tmp_sum & 0x0f) - -byte_fffbd = ((pll_checksum & 0x0f) << 4) | 0x0f - - .section ".a9123_crossbar_config", "a", @progbits - - .skip 0x3fdf0 - 0x3fd00, 0xff - -.previous - - .section ".a9123_strap_1", "a", @progbits - - .byte byte_fffb6, byte_fffb7 - -.previous - - .section ".a9123_strap_2", "a", @progbits - - .byte byte_fffbb, byte_fffbc, byte_fffbd, byte_fffbe, byte_fffbf - -.previous diff --git a/src/cpu/dmp/vortex86ex/chipset_bootblock.inc b/src/cpu/dmp/vortex86ex/chipset_bootblock.inc deleted file mode 100644 index bdcda1d40f..0000000000 --- a/src/cpu/dmp/vortex86ex/chipset_bootblock.inc +++ /dev/null @@ -1,2 +0,0 @@ -#include "biosdata.inc" -#include "biosdata_ex.inc" -- cgit v1.2.3