From fd14d4414aab2b196bdf4499a3590187bf9c782d Mon Sep 17 00:00:00 2001 From: "Ronald G. Minnich" Date: Wed, 14 Jun 2006 13:56:28 +0000 Subject: remove erroneous cache disable. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2320 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1 --- src/cpu/amd/model_gx2/cpureginit.c | 14 +++++++++++--- 1 file changed, 11 insertions(+), 3 deletions(-) (limited to 'src/cpu/amd') diff --git a/src/cpu/amd/model_gx2/cpureginit.c b/src/cpu/amd/model_gx2/cpureginit.c index 779669c34a..5e786910c5 100644 --- a/src/cpu/amd/model_gx2/cpureginit.c +++ b/src/cpu/amd/model_gx2/cpureginit.c @@ -231,9 +231,13 @@ cpuRegInit (void){ wrmsr(msrnum, msr); } -/* */ -/* Cache Overides*/ -/* */ +#if 0 + /* */ + /* Cache Overides*/ + /* */ + /* This code disables the data cache. Don't execute this + * unless you're testing something. + */ /* Allow NVRam to override DM Setup*/ /*if (getnvram( TOKEN_CACHE_DM_MODE) != 1) {*/ { @@ -243,6 +247,9 @@ cpuRegInit (void){ msr.lo |= DM_CONFIG0_LOWER_DCDIS_SET; wrmsr(msrnum, msr); } + /* This code disables the instruction cache. Don't execute + * this unless you're testing something. + */ /* Allow NVRam to override IM Setup*/ /*if (getnvram( TOKEN_CACHE_IM_MODE) ==1) {*/ { @@ -251,6 +258,7 @@ cpuRegInit (void){ msr.lo |= IM_CONFIG_LOWER_ICD_SET; wrmsr(msrnum, msr); } +#endif } -- cgit v1.2.3