From ed1f9a75b30c0080dc057240b5bac726a274a062 Mon Sep 17 00:00:00 2001 From: "Ronald G. Minnich" Date: Wed, 23 Nov 2005 05:09:42 +0000 Subject: missed these. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2093 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1 --- src/cpu/amd/model_fxx/microcode_rev_c.h | 149 ++++++++++++++++++++++++++++++++ src/cpu/amd/model_fxx/microcode_rev_d.h | 148 +++++++++++++++++++++++++++++++ src/cpu/amd/model_fxx/microcode_rev_e.h | 149 ++++++++++++++++++++++++++++++++ 3 files changed, 446 insertions(+) create mode 100644 src/cpu/amd/model_fxx/microcode_rev_c.h create mode 100644 src/cpu/amd/model_fxx/microcode_rev_d.h create mode 100644 src/cpu/amd/model_fxx/microcode_rev_e.h (limited to 'src/cpu/amd') diff --git a/src/cpu/amd/model_fxx/microcode_rev_c.h b/src/cpu/amd/model_fxx/microcode_rev_c.h new file mode 100644 index 0000000000..f102d37d0f --- /dev/null +++ b/src/cpu/amd/model_fxx/microcode_rev_c.h @@ -0,0 +1,149 @@ +/* + ============================================================ + (c) Advanced Micro Devices, Inc., 2004-2005 + + The enclosed microcode is intended to be used with AMD + Microprocessors. You may copy, view and install the + enclosed microcode only for development and deployment of + firmware, BIOS, or operating system code for computer + systems that contain AMD processors. You are not + authorized to use the enclosed microcode for any other + purpose. + + THE MICROCODE IS PROVIDED "AS IS" WITHOUT ANY EXPRESS OR + IMPLIED WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO + WARRANTIES OF MERCHANTABILITY, NON- INFRINGEMENT, + TITLE,FITNESS FOR ANY PARTICULAR PURPOSE, OR WARRANTIES + ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + AMD does not assume any responsibility for any errors which + may appear in this microcode or any other related + information provided to you by AMD, or result from use of + this microcode. AMD is not obligated to furnish, support, + or make any further information, software, technical + information, know-how, or show-how available related to this + microcode. + + The microcode is provided with "RESTRICTED RIGHTS." Use, + duplication, or disclosure by the U.S. Government is subject + to the restrictions as set forth in FAR 52.227-14 and + DFAR252.227-7013, et seq., or its successor. Use of the + microcode by the U.S. Government constitutes + acknowledgement of AMD's proprietary rights in them. + ============================================================ +*/ + +/* Microcode patch for Cx provessors that fixes Errata 109 */ + 0x04, 0x20, 0x19, 0x07, 0x47, 0x00, 0x00, 0x00, 0x00, 0x80, 0x20, 0x00, 0x53, 0xdd, 0xbe, 0x2e, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x4a, 0x00, 0x00, 0x00, 0x00, 0xaa, 0xaa, 0xaa, + 0x44, 0x06, 0x00, 0x00, 0x40, 0x01, 0x00, 0x00, 0xb4, 0x04, 0x00, 0x00, 0xba, 0x04, 0x00, 0x00, + 0x84, 0x08, 0x00, 0x00, 0x45, 0x07, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xfb, 0xff, 0x00, 0xc3, 0x35, 0x90, 0xfd, 0xf8, 0x7b, 0xfe, 0xa9, 0x0f, 0xff, 0x00, 0x3f, + 0xfe, 0xdf, 0xff, 0xc7, 0x1e, 0xbc, 0x03, 0x3c, 0x80, 0x24, 0xd6, 0x00, 0x14, 0xfe, 0xff, 0xff, + 0xfe, 0xe1, 0x1f, 0xeb, 0x4c, 0xf6, 0x3c, 0xff, 0x9f, 0x87, 0x7f, 0x80, 0x27, 0x60, 0x26, 0xf0, + 0x74, 0x1d, 0xfe, 0x18, 0x00, 0x20, 0x12, 0x6b, 0xcf, 0xfb, 0xff, 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You may copy, view and install the + enclosed microcode only for development and deployment of + firmware, BIOS, or operating system code for computer + systems that contain AMD processors. You are not + authorized to use the enclosed microcode for any other + purpose. + + THE MICROCODE IS PROVIDED "AS IS" WITHOUT ANY EXPRESS OR + IMPLIED WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO + WARRANTIES OF MERCHANTABILITY, NON- INFRINGEMENT, + TITLE,FITNESS FOR ANY PARTICULAR PURPOSE, OR WARRANTIES + ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + AMD does not assume any responsibility for any errors which + may appear in this microcode or any other related + information provided to you by AMD, or result from use of + this microcode. AMD is not obligated to furnish, support, + or make any further information, software, technical + information, know-how, or show-how available related to this + microcode. + + The microcode is provided with "RESTRICTED RIGHTS." Use, + duplication, or disclosure by the U.S. Government is subject + to the restrictions as set forth in FAR 52.227-14 and + DFAR252.227-7013, et seq., or its successor. Use of the + microcode by the U.S. Government constitutes + acknowledgement of AMD's proprietary rights in them. + ============================================================ +*/ + +/* Rev Dx Microcode Patch for Errata 109 */ + 0x04, 0x20, 0x25, 0x02, 0x41, 0x00, 0x00, 0x00, 0x00, 0x80, 0x20, 0x00, 0xfd, 0x6a, 0x5a, 0x3e, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x50, 0x01, 0x00, 0x00, 0x00, 0xaa, 0xaa, 0xaa, + 0x44, 0x06, 0x00, 0x00, 0x40, 0x01, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xfb, 0xff, 0x00, 0xc3, 0x35, 0x90, 0xfd, 0xf8, 0x7b, 0xfe, 0xa9, 0x0f, 0xff, 0x00, 0x3f, + 0xfe, 0xdf, 0xff, 0xc7, 0x1e, 0xbc, 0x03, 0x3c, 0x80, 0xc8, 0xd5, 0x00, 0x14, 0xfe, 0xff, 0xff, + 0xfe, 0xe1, 0x1f, 0xeb, 0x4c, 0xf6, 0x3c, 0xff, 0x9f, 0x87, 0x7f, 0x80, 0x27, 0x60, 0x26, 0xf0, + 0x74, 0x1d, 0xfe, 0x18, 0x00, 0x20, 0xe4, 0x6a, 0xcf, 0xfb, 0xff, 0xe7, 0xf0, 0xf3, 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You may copy, view and install the + enclosed microcode only for development and deployment of + firmware, BIOS, or operating system code for computer + systems that contain AMD processors. You are not + authorized to use the enclosed microcode for any other + purpose. + + THE MICROCODE IS PROVIDED "AS IS" WITHOUT ANY EXPRESS OR + IMPLIED WARRANTY OF ANY KIND, INCLUDING BUT NOT LIMITED TO + WARRANTIES OF MERCHANTABILITY, NON- INFRINGEMENT, + TITLE,FITNESS FOR ANY PARTICULAR PURPOSE, OR WARRANTIES + ARISING FROM CONDUCT, COURSE OF DEALING, OR USAGE OF TRADE. + AMD does not assume any responsibility for any errors which + may appear in this microcode or any other related + information provided to you by AMD, or result from use of + this microcode. AMD is not obligated to furnish, support, + or make any further information, software, technical + information, know-how, or show-how available related to this + microcode. + + The microcode is provided with "RESTRICTED RIGHTS." Use, + duplication, or disclosure by the U.S. Government is subject + to the restrictions as set forth in FAR 52.227-14 and + DFAR252.227-7013, et seq., or its successor. Use of the + microcode by the U.S. Government constitutes + acknowledgement of AMD's proprietary rights in them. + ============================================================ +*/ + +/* Microcode Patch for Dual-Core Ex processors that fixes Errata 123*/ + 0x05, 0x20, 0x28, 0x04, 0x4d, 0x00, 0x00, 0x00, 0x00, 0x80, 0x20, 0x01, 0x6b, 0x59, 0x94, 0xc2, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x02, 0x00, 0x00, 0x01, 0xaa, 0xaa, 0xaa, + 0xa8, 0x02, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0x80, 0xff, 0xff, 0xc0, 0xc3, 0x3d, 0x80, 0xef, 0xfc, 0xbf, 0xff, 0x7b, 0x0f, 0xff, 0x00, 0x3f, + 0xf0, 0x1f, 0xf8, 0x07, 0x37, 0xfc, 0x03, 0xf8, 0xc0, 0x3b, 0xc8, 0x00, 0x80, 0xff, 0xc0, 0x3f, + 0xbf, 0xe1, 0x1f, 0xc0, 0x00, 0xfe, 0x03, 0xff, 0xff, 0x86, 0x7f, 0x00, 0x03, 0xf8, 0x0f, 0xfc, + 0xfc, 0x1b, 0xfe, 0x01, 0x00, 0xe0, 0xff, 0x7b, 0x1f, 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