From 9de8ab9acec90d36aa23c63f3f46bca3b628d0f6 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Sat, 9 Sep 2017 16:51:34 +0300 Subject: AGESA_LEGACY: Apply final cleanup and file removals MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit With no boards left using AGESA_LEGACY, wipe out remains of that everywhere in the tree. Change-Id: I0ddc1f400e56e42fe8a43b4766195e3a187dcea6 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/18633 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer --- src/cpu/amd/agesa/Kconfig | 13 +-- src/cpu/amd/agesa/Makefile.inc | 6 -- src/cpu/amd/agesa/amd_late_init.c | 42 -------- src/cpu/amd/agesa/cache_as_ram_legacy.inc | 170 ------------------------------ src/cpu/amd/agesa/family12/Makefile.inc | 2 +- src/cpu/amd/agesa/family12/romstage.c | 32 ------ src/cpu/amd/agesa/family14/Makefile.inc | 2 +- src/cpu/amd/agesa/family14/romstage.c | 45 -------- src/cpu/amd/agesa/family15/Makefile.inc | 2 +- src/cpu/amd/agesa/family15/romstage.c | 27 +---- src/cpu/amd/agesa/family15tn/Makefile.inc | 1 - src/cpu/amd/agesa/family15tn/romstage.c | 62 ----------- src/cpu/amd/agesa/family16kb/Makefile.inc | 1 - src/cpu/amd/agesa/family16kb/romstage.c | 64 ----------- 14 files changed, 7 insertions(+), 462 deletions(-) delete mode 100644 src/cpu/amd/agesa/amd_late_init.c delete mode 100644 src/cpu/amd/agesa/cache_as_ram_legacy.inc delete mode 100644 src/cpu/amd/agesa/family15tn/romstage.c delete mode 100644 src/cpu/amd/agesa/family16kb/romstage.c (limited to 'src/cpu/amd') diff --git a/src/cpu/amd/agesa/Kconfig b/src/cpu/amd/agesa/Kconfig index 602a9b0528..77db54cb58 100644 --- a/src/cpu/amd/agesa/Kconfig +++ b/src/cpu/amd/agesa/Kconfig @@ -30,21 +30,10 @@ config CPU_AMD_AGESA select UDELAY_LAPIC select LAPIC_MONOTONIC_TIMER select SPI_FLASH if HAVE_ACPI_RESUME - select POSTCAR_STAGE if !AGESA_LEGACY_WRAPPER + select POSTCAR_STAGE if CPU_AMD_AGESA -config AGESA_LEGACY - def_bool n - -config AGESA_LEGACY_WRAPPER - bool - default AGESA_LEGACY - -config AGESA_NO_LEGACY - bool - default !AGESA_LEGACY - config XIP_ROM_SIZE hex default 0x100000 diff --git a/src/cpu/amd/agesa/Makefile.inc b/src/cpu/amd/agesa/Makefile.inc index 470e62f25d..e581661c06 100644 --- a/src/cpu/amd/agesa/Makefile.inc +++ b/src/cpu/amd/agesa/Makefile.inc @@ -18,12 +18,6 @@ subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY15) += family15 subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY15_TN) += family15tn subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY16_KB) += family16kb -ifeq ($(CONFIG_AGESA_LEGACY), y) -cpu_incs-y += $(src)/cpu/amd/agesa/cache_as_ram_legacy.inc -endif - -ramstage-$(CONFIG_AGESA_LEGACY_WRAPPER) += amd_late_init.c - ifeq ($(CONFIG_HAVE_ACPI_RESUME), y) $(obj)/coreboot_s3nv.rom: $(obj)/config.h diff --git a/src/cpu/amd/agesa/amd_late_init.c b/src/cpu/amd/agesa/amd_late_init.c deleted file mode 100644 index 9bb6b2784e..0000000000 --- a/src/cpu/amd/agesa/amd_late_init.c +++ /dev/null @@ -1,42 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include - -#include - -#if IS_ENABLED(CONFIG_AMD_SB_CIMX) -#include -#endif - -static void agesawrapper_post_device(void *unused) -{ - if (acpi_is_wakeup_s3()) - return; - - agesawrapper_amdinitlate(); - -#if IS_ENABLED(CONFIG_AMD_SB_CIMX) - sb_Late_Post(); -#endif - if (!acpi_s3_resume_allowed()) - return; - - agesawrapper_amdS3Save(); -} - -BOOT_STATE_INIT_ENTRY(BS_POST_DEVICE, BS_ON_EXIT, - agesawrapper_post_device, NULL); diff --git a/src/cpu/amd/agesa/cache_as_ram_legacy.inc b/src/cpu/amd/agesa/cache_as_ram_legacy.inc deleted file mode 100644 index 55480070c9..0000000000 --- a/src/cpu/amd/agesa/cache_as_ram_legacy.inc +++ /dev/null @@ -1,170 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/****************************************************************************** - * AMD Generic Encapsulated Software Architecture - * - * $Workfile:: cache_as_ram.inc - * - * Description: cache_as_ram.inc - AGESA Module Entry Point for GCC complier - * - ****************************************************************************** - */ - -#include "gcccar.inc" -#include - -/* - * XMM map: - * xmm0: BIST - * xmm1: backup ebx -- cpu_init_detected - */ - -.code32 -.globl cache_as_ram_setup, disable_cache_as_ram, cache_as_ram_setup_out - -cache_as_ram_setup: - - post_code(0xa0) - - /* enable SSE2 128bit instructions */ - /* Turn on OSFXSR [BIT9] and OSXMMEXCPT [BIT10] onto CR4 register */ - - movl %cr4, %eax - orl $(3 << 9), %eax - movl %eax, %cr4 - - /* Get the cpu_init_detected */ - mov $1, %eax - cpuid - shr $24, %ebx - - /* Save the BIST result */ - cvtsi2sd %ebp, %xmm0 - - /* for normal part %ebx already contain cpu_init_detected from fallback call */ - - /* Save the cpu_init_detected */ - cvtsi2sd %ebx, %xmm1 - - post_code(0xa1) - - AMD_ENABLE_STACK - - /* Align the stack. */ - and $0xFFFFFFF0, %esp - -#ifdef __x86_64__ - /* switch to 64 bit long mode */ - mov %esi, %ecx - add $0, %ecx # core number - xor %eax, %eax - lea (0x1000+0x23)(%ecx), %edi - mov %edi, (%ecx) - mov %eax, 4(%ecx) - - lea 0x1000(%ecx), %edi - movl $0x000000e3, 0x00(%edi) - movl %eax, 0x04(%edi) - movl $0x400000e3, 0x08(%edi) - movl %eax, 0x0c(%edi) - movl $0x800000e3, 0x10(%edi) - movl %eax, 0x14(%edi) - movl $0xc00000e3, 0x18(%edi) - movl %eax, 0x1c(%edi) - - # load ROM based identity mapped page tables - mov %ecx, %eax - mov %eax, %cr3 - - # enable PAE - mov %cr4, %eax - bts $5, %eax - mov %eax, %cr4 - - # enable long mode - mov $0xC0000080, %ecx - rdmsr - bts $8, %eax - wrmsr - - # enable paging - mov %cr0, %eax - bts $31, %eax - mov %eax, %cr0 - - # use call far to switch to 64-bit code segment - ljmp $0x18, $1f -1: - /* Pass the cpu_init_detected */ - cvtsd2si %xmm1, %esi - - /* Pass the BIST result */ - cvtsd2si %xmm0, %edi - - - .code64 - call cache_as_ram_main - .code32 - -#else - - /* Restore the BIST result */ - cvtsd2si %xmm0, %edx - - /* Restore the cpu_init_detected */ - cvtsd2si %xmm1, %ebx - - /* Must maintain 16-byte stack alignment here. */ - pushl $0x0 - pushl $0x0 - pushl %ebx /* init detected */ - pushl %edx /* bist */ - call cache_as_ram_main -#endif - - /* Should never see this postcode */ - post_code(0xaf) -stop: - jmp stop - -disable_cache_as_ram: - /* Save return stack */ - movd 0(%esp), %xmm1 - movd %esp, %xmm0 - - /* Disable cache */ - movl %cr0, %eax - orl $CR0_CacheDisable, %eax - movl %eax, %cr0 - - AMD_DISABLE_STACK - - /* enable cache */ - movl %cr0, %eax - andl $0x9fffffff, %eax - movl %eax, %cr0 - xorl %eax, %eax - - /* Restore the return stack */ - wbinvd - movd %xmm0, %esp - movd %xmm1, (%esp) - ret - -cache_as_ram_setup_out: -#ifdef __x86_64__ -.code64 -#endif diff --git a/src/cpu/amd/agesa/family12/Makefile.inc b/src/cpu/amd/agesa/family12/Makefile.inc index 5673c6b502..1a7465d81f 100644 --- a/src/cpu/amd/agesa/family12/Makefile.inc +++ b/src/cpu/amd/agesa/family12/Makefile.inc @@ -28,7 +28,7 @@ #***************************************************************************** romstage-y += fixme.c -romstage-$(CONFIG_AGESA_NO_LEGACY) += romstage.c +romstage-y += romstage.c ramstage-y += fixme.c ramstage-y += chip_name.c diff --git a/src/cpu/amd/agesa/family12/romstage.c b/src/cpu/amd/agesa/family12/romstage.c index 2a183270d7..9d617efe4b 100644 --- a/src/cpu/amd/agesa/family12/romstage.c +++ b/src/cpu/amd/agesa/family12/romstage.c @@ -14,12 +14,7 @@ * GNU General Public License for more details. */ -#include -#include - -#include #include -#include #include "sb_cimx.h" #include "SbPlatform.h" @@ -33,30 +28,3 @@ void platform_once(struct sysinfo *cb) board_BeforeAgesa(cb); } - -void agesa_main(struct sysinfo *cb) -{ - post_code(0x36); - agesawrapper_amdinitreset(); - - post_code(0x37); - agesawrapper_amdinitearly(); - - printk(BIOS_INFO, "Normal boot\n"); - - post_code(0x38); - agesawrapper_amdinitpost(); -} - -void agesa_postcar(struct sysinfo *cb) -{ - printk(BIOS_INFO, "Normal boot postcar\n"); - - post_code(0x39); - printk(BIOS_DEBUG, "sb_before_pci_init "); - sb_before_pci_init(); - printk(BIOS_DEBUG, "passed.\n"); - - post_code(0x40); - agesawrapper_amdinitenv(); -} diff --git a/src/cpu/amd/agesa/family14/Makefile.inc b/src/cpu/amd/agesa/family14/Makefile.inc index 71d15fbbf6..3da8dd599b 100644 --- a/src/cpu/amd/agesa/family14/Makefile.inc +++ b/src/cpu/amd/agesa/family14/Makefile.inc @@ -14,7 +14,7 @@ # romstage-y += fixme.c -romstage-$(CONFIG_AGESA_NO_LEGACY) += romstage.c +romstage-y += romstage.c ramstage-y += fixme.c ramstage-y += chip_name.c diff --git a/src/cpu/amd/agesa/family14/romstage.c b/src/cpu/amd/agesa/family14/romstage.c index 53e6a1c623..7fd522fb1e 100644 --- a/src/cpu/amd/agesa/family14/romstage.c +++ b/src/cpu/amd/agesa/family14/romstage.c @@ -14,12 +14,8 @@ * GNU General Public License for more details. */ -#include -#include -#include #include -#include #include @@ -29,44 +25,3 @@ void platform_once(struct sysinfo *cb) board_BeforeAgesa(cb); } - -void agesa_main(struct sysinfo *cb) -{ - post_code(0x37); - agesawrapper_amdinitreset(); - - post_code(0x39); - agesawrapper_amdinitearly(); - - if (!cb->s3resume) { - printk(BIOS_INFO, "Normal boot\n"); - - post_code(0x40); - agesawrapper_amdinitpost(); - } else { - printk(BIOS_INFO, "S3 detected\n"); - - post_code(0x60); - agesawrapper_amdinitresume(); - } -} - -void agesa_postcar(struct sysinfo *cb) -{ - if (!cb->s3resume) { - printk(BIOS_INFO, "Normal boot postcar\n"); - - post_code(0x41); - agesawrapper_amdinitenv(); - - post_code(0x42); - amd_initenv(); - } else { - printk(BIOS_INFO, "S3 resume postcar\n"); - - post_code(0x61); - agesawrapper_amds3laterestore(); - - post_code(0x62); - } -} diff --git a/src/cpu/amd/agesa/family15/Makefile.inc b/src/cpu/amd/agesa/family15/Makefile.inc index d7cdff7a30..d01cb2aec5 100644 --- a/src/cpu/amd/agesa/family15/Makefile.inc +++ b/src/cpu/amd/agesa/family15/Makefile.inc @@ -22,7 +22,7 @@ subdirs-y += ../../../x86/pae subdirs-y += ../../../x86/smm romstage-y += fixme.c -romstage-$(CONFIG_AGESA_NO_LEGACY) += romstage.c +romstage-y += romstage.c ramstage-y += fixme.c ramstage-y += chip_name.c diff --git a/src/cpu/amd/agesa/family15/romstage.c b/src/cpu/amd/agesa/family15/romstage.c index 7e65f81e1d..46c03910f7 100644 --- a/src/cpu/amd/agesa/family15/romstage.c +++ b/src/cpu/amd/agesa/family15/romstage.c @@ -20,8 +20,6 @@ #include #include -#include -#include #include #include "northbridge/amd/agesa/family15/reset_test.h" @@ -43,15 +41,8 @@ void platform_once(struct sysinfo *cb) board_BeforeAgesa(cb); } -void agesa_main(struct sysinfo *cb) -{ - post_code(0x37); - agesawrapper_amdinitreset(); - - post_code(0x3B); - agesawrapper_amdinitearly(); - - post_code(0x3C); +#if 0 + /* Was between EARLY and POST */ nb_Ht_Init(); post_code(0x3D); @@ -63,16 +54,4 @@ void agesa_main(struct sysinfo *cb) die("After soft_reset - shouldn't see this message!!!\n"); } - post_code(0x40); - agesawrapper_amdinitpost(); - - printk(BIOS_INFO, "Normal boot\n"); -} - -void agesa_postcar(struct sysinfo *cb) -{ - printk(BIOS_INFO, "Normal boot postcar\n"); - - post_code(0x41); - agesawrapper_amdinitenv(); -} +#endif diff --git a/src/cpu/amd/agesa/family15tn/Makefile.inc b/src/cpu/amd/agesa/family15tn/Makefile.inc index 4fcaff7405..98a7050c21 100644 --- a/src/cpu/amd/agesa/family15tn/Makefile.inc +++ b/src/cpu/amd/agesa/family15tn/Makefile.inc @@ -14,7 +14,6 @@ # romstage-y += fixme.c -romstage-$(CONFIG_AGESA_NO_LEGACY) += romstage.c ramstage-y += fixme.c ramstage-y += chip_name.c diff --git a/src/cpu/amd/agesa/family15tn/romstage.c b/src/cpu/amd/agesa/family15tn/romstage.c deleted file mode 100644 index fcf2f17fe5..0000000000 --- a/src/cpu/amd/agesa/family15tn/romstage.c +++ /dev/null @@ -1,62 +0,0 @@ - -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * Copyright (C) 2017 Kyösti Mälkki - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include - -#include -#include -#include - -void agesa_main(struct sysinfo *cb) -{ - post_code(0x37); - agesawrapper_amdinitreset(); - - post_code(0x39); - agesawrapper_amdinitearly(); - - if (!cb->s3resume) { - printk(BIOS_INFO, "Normal boot\n"); - - post_code(0x40); - agesawrapper_amdinitpost(); - } else { - printk(BIOS_INFO, "S3 detected\n"); - - post_code(0x60); - agesawrapper_amdinitresume(); - } -} - -void agesa_postcar(struct sysinfo *cb) -{ - if (!cb->s3resume) { - printk(BIOS_INFO, "Normal boot postcar\n"); - - post_code(0x41); - agesawrapper_amdinitenv(); - } else { - printk(BIOS_INFO, "S3 resume postcar\n"); - - post_code(0x61); - amd_initcpuio(); - - post_code(0x62); - agesawrapper_amds3laterestore(); - } -} diff --git a/src/cpu/amd/agesa/family16kb/Makefile.inc b/src/cpu/amd/agesa/family16kb/Makefile.inc index 31c3ecfabc..9367b458a3 100644 --- a/src/cpu/amd/agesa/family16kb/Makefile.inc +++ b/src/cpu/amd/agesa/family16kb/Makefile.inc @@ -14,7 +14,6 @@ # romstage-y += fixme.c -romstage-$(CONFIG_AGESA_NO_LEGACY) += romstage.c ramstage-y += fixme.c ramstage-y += chip_name.c diff --git a/src/cpu/amd/agesa/family16kb/romstage.c b/src/cpu/amd/agesa/family16kb/romstage.c deleted file mode 100644 index 3f9afce080..0000000000 --- a/src/cpu/amd/agesa/family16kb/romstage.c +++ /dev/null @@ -1,64 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * Copyright (C) 2017 Kyösti Mälkki - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include - -#include -#include -#include - -void agesa_main(struct sysinfo *cb) -{ - post_code(0x37); - agesawrapper_amdinitreset(); - - post_code(0x39); - agesawrapper_amdinitearly(); - - if (!cb->s3resume) { - printk(BIOS_INFO, "Normal boot\n"); - - post_code(0x40); - agesawrapper_amdinitpost(); - - } else { - printk(BIOS_INFO, "S3 detected\n"); - - post_code(0x60); - agesawrapper_amdinitresume(); - } -} - -void agesa_postcar(struct sysinfo *cb) -{ - if (!cb->s3resume) { - printk(BIOS_INFO, "Normal boot postcar\n"); - - post_code(0x41); - agesawrapper_amdinitenv(); - } else { - printk(BIOS_INFO, "S3 resume postcar\n"); - - post_code(0x61); - amd_initcpuio(); - - post_code(0x62); - agesawrapper_amds3laterestore(); - - post_code(0x63); - } -} -- cgit v1.2.3