From 7369e83de1e42138245e728304dc743feaa08c32 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Mon, 17 Jul 2017 23:00:31 +0300 Subject: AGESA: Add romstage timestamps MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Experiments on f14 f15tn and 16kb suggest that TSC counter value shifts at end of raminit. To account for this all previously stored values in timestamp table are also divided by 4. Change-Id: I47584997bf456e35cf0aeb97ef255748745c30ee Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/20622 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Aaron Durbin --- src/cpu/amd/agesa/romstage.c | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'src/cpu/amd') diff --git a/src/cpu/amd/agesa/romstage.c b/src/cpu/amd/agesa/romstage.c index cb98e7b6d3..a7d2ff90b7 100644 --- a/src/cpu/amd/agesa/romstage.c +++ b/src/cpu/amd/agesa/romstage.c @@ -26,6 +26,7 @@ #include #include #include +#include #include #include @@ -60,6 +61,9 @@ void * asmlinkage romstage_main(unsigned long bist) if ((initial_apic_id == 0) && boot_cpu()) { + timestamp_init(timestamp_get()); + timestamp_add_now(TS_START_ROMSTAGE); + platform_once(cb); console_init(); @@ -77,11 +81,17 @@ void * asmlinkage romstage_main(unsigned long bist) agesa_execute_state(cb, AMD_INIT_EARLY); + timestamp_add_now(TS_BEFORE_INITRAM); + if (!cb->s3resume) agesa_execute_state(cb, AMD_INIT_POST); else agesa_execute_state(cb, AMD_INIT_RESUME); + /* FIXME: Detect if TSC frequency changed during raminit? */ + timestamp_rescale_table(1, 4); + timestamp_add_now(TS_AFTER_INITRAM); + } else { agesa_main(cb); -- cgit v1.2.3