From 7076aa5745babc188275a837797d5f0f0b7db5d8 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Sat, 2 Sep 2017 16:20:15 +0300 Subject: AGESA: Rename assembly from .inc to .S MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: I5f90df92e0ac27e98edf23784eeec5618d150430 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/21378 Tested-by: build bot (Jenkins) Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Martin Roth --- src/cpu/amd/agesa/Makefile.inc | 2 +- src/cpu/amd/agesa/cache_as_ram.S | 134 +++++++++++++++++++++++++++++++++++++ src/cpu/amd/agesa/cache_as_ram.inc | 133 ------------------------------------ src/cpu/amd/pi/Makefile.inc | 2 +- 4 files changed, 136 insertions(+), 135 deletions(-) create mode 100644 src/cpu/amd/agesa/cache_as_ram.S delete mode 100644 src/cpu/amd/agesa/cache_as_ram.inc (limited to 'src/cpu/amd') diff --git a/src/cpu/amd/agesa/Makefile.inc b/src/cpu/amd/agesa/Makefile.inc index 1d5e705277..d9c5f704e0 100644 --- a/src/cpu/amd/agesa/Makefile.inc +++ b/src/cpu/amd/agesa/Makefile.inc @@ -24,7 +24,7 @@ ramstage-y += s3_mtrr.c ifeq ($(CONFIG_AGESA_LEGACY), y) cpu_incs-y += $(src)/cpu/amd/agesa/cache_as_ram_legacy.inc else -cpu_incs-y += $(src)/cpu/amd/agesa/cache_as_ram.inc +cpu_incs-y += $(src)/cpu/amd/agesa/cache_as_ram.S romstage-y += romstage.c endif diff --git a/src/cpu/amd/agesa/cache_as_ram.S b/src/cpu/amd/agesa/cache_as_ram.S new file mode 100644 index 0000000000..b96a5e70e4 --- /dev/null +++ b/src/cpu/amd/agesa/cache_as_ram.S @@ -0,0 +1,134 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/****************************************************************************** + * AMD Generic Encapsulated Software Architecture + * + * $Workfile:: cache_as_ram.S + * + * Description: cache_as_ram.S - AGESA Module Entry Point for GCC complier + * + ****************************************************************************** + */ + +#include "gcccar.inc" +#include +#include + +.code32 +.globl _cache_as_ram_setup, _cache_as_ram_setup_end + +_cache_as_ram_setup: + + /* Preserve BIST. */ + movd %eax, %mm0 + + post_code(0xa0) + + /* enable SSE2 128bit instructions */ + /* Turn on OSFXSR [BIT9] and OSXMMEXCPT [BIT10] onto CR4 register */ + + movl %cr4, %eax + orl $(3 << 9), %eax + movl %eax, %cr4 + + post_code(0xa1) + + AMD_ENABLE_STACK + + /* Align the stack. */ + and $0xFFFFFFF0, %esp + +#ifdef __x86_64__ + /* switch to 64 bit long mode */ + mov %esi, %ecx + add $0, %ecx # core number + xor %eax, %eax + lea (0x1000+0x23)(%ecx), %edi + mov %edi, (%ecx) + mov %eax, 4(%ecx) + + lea 0x1000(%ecx), %edi + movl $0x000000e3, 0x00(%edi) + movl %eax, 0x04(%edi) + movl $0x400000e3, 0x08(%edi) + movl %eax, 0x0c(%edi) + movl $0x800000e3, 0x10(%edi) + movl %eax, 0x14(%edi) + movl $0xc00000e3, 0x18(%edi) + movl %eax, 0x1c(%edi) + + # load ROM based identity mapped page tables + mov %ecx, %eax + mov %eax, %cr3 + + # enable PAE + mov %cr4, %eax + bts $5, %eax + mov %eax, %cr4 + + # enable long mode + mov $0xC0000080, %ecx + rdmsr + bts $8, %eax + wrmsr + + # enable paging + mov %cr0, %eax + bts $31, %eax + mov %eax, %cr0 + + # use call far to switch to 64-bit code segment + ljmp $0x18, $1f +1: + +#endif + + call early_all_cores + + /* Must maintain 16-byte stack alignment here. */ + pushl $0x0 + pushl $0x0 + pushl $0x0 + movd %mm0, %eax /* bist */ + pushl %eax + call romstage_main + movl %eax, %esp + +/* Register %esp is new stacktop for remaining of romstage. + * It is the only register preserved in AMD_DISABLE_STACK. + */ + +disable_cache_as_ram: + /* Disable cache */ + movl %cr0, %eax + orl $CR0_CacheDisable, %eax + movl %eax, %cr0 + + AMD_DISABLE_STACK + + /* enable cache */ + movl %cr0, %eax + andl $0x9fffffff, %eax + movl %eax, %cr0 + + call romstage_after_car + + /* Should never see this postcode */ + post_code(0xaf) +stop: + jmp stop + +_cache_as_ram_setup_end: diff --git a/src/cpu/amd/agesa/cache_as_ram.inc b/src/cpu/amd/agesa/cache_as_ram.inc deleted file mode 100644 index cfad2f7d1a..0000000000 --- a/src/cpu/amd/agesa/cache_as_ram.inc +++ /dev/null @@ -1,133 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/****************************************************************************** - * AMD Generic Encapsulated Software Architecture - * - * $Workfile:: cache_as_ram.inc - * - * Description: cache_as_ram.inc - AGESA Module Entry Point for GCC complier - * - ****************************************************************************** - */ - -#include "gcccar.inc" -#include - -.code32 -.globl cache_as_ram_setup, cache_as_ram_setup_out - -cache_as_ram_setup: - - /* Preserve BIST. */ - movd %eax, %mm0 - - post_code(0xa0) - - /* enable SSE2 128bit instructions */ - /* Turn on OSFXSR [BIT9] and OSXMMEXCPT [BIT10] onto CR4 register */ - - movl %cr4, %eax - orl $(3 << 9), %eax - movl %eax, %cr4 - - post_code(0xa1) - - AMD_ENABLE_STACK - - /* Align the stack. */ - and $0xFFFFFFF0, %esp - -#ifdef __x86_64__ - /* switch to 64 bit long mode */ - mov %esi, %ecx - add $0, %ecx # core number - xor %eax, %eax - lea (0x1000+0x23)(%ecx), %edi - mov %edi, (%ecx) - mov %eax, 4(%ecx) - - lea 0x1000(%ecx), %edi - movl $0x000000e3, 0x00(%edi) - movl %eax, 0x04(%edi) - movl $0x400000e3, 0x08(%edi) - movl %eax, 0x0c(%edi) - movl $0x800000e3, 0x10(%edi) - movl %eax, 0x14(%edi) - movl $0xc00000e3, 0x18(%edi) - movl %eax, 0x1c(%edi) - - # load ROM based identity mapped page tables - mov %ecx, %eax - mov %eax, %cr3 - - # enable PAE - mov %cr4, %eax - bts $5, %eax - mov %eax, %cr4 - - # enable long mode - mov $0xC0000080, %ecx - rdmsr - bts $8, %eax - wrmsr - - # enable paging - mov %cr0, %eax - bts $31, %eax - mov %eax, %cr0 - - # use call far to switch to 64-bit code segment - ljmp $0x18, $1f -1: - -#endif - - call early_all_cores - - /* Must maintain 16-byte stack alignment here. */ - pushl $0x0 - pushl $0x0 - pushl $0x0 - movd %mm0, %eax /* bist */ - pushl %eax - call romstage_main - movl %eax, %esp - -/* Register %esp is new stacktop for remaining of romstage. - * It is the only register preserved in AMD_DISABLE_STACK. - */ - -disable_cache_as_ram: - /* Disable cache */ - movl %cr0, %eax - orl $CR0_CacheDisable, %eax - movl %eax, %cr0 - - AMD_DISABLE_STACK - - /* enable cache */ - movl %cr0, %eax - andl $0x9fffffff, %eax - movl %eax, %cr0 - - call romstage_after_car - - /* Should never see this postcode */ - post_code(0xaf) -stop: - jmp stop - -cache_as_ram_setup_out: diff --git a/src/cpu/amd/pi/Makefile.inc b/src/cpu/amd/pi/Makefile.inc index 3171bb5d67..af24b48001 100644 --- a/src/cpu/amd/pi/Makefile.inc +++ b/src/cpu/amd/pi/Makefile.inc @@ -17,7 +17,7 @@ subdirs-$(CONFIG_CPU_AMD_PI_00630F01) += 00630F01 subdirs-$(CONFIG_CPU_AMD_PI_00730F01) += 00730F01 subdirs-$(CONFIG_CPU_AMD_PI_00660F01) += 00660F01 -cpu_incs-y += $(src)/cpu/amd/agesa/cache_as_ram.inc +cpu_incs-y += $(src)/cpu/amd/agesa/cache_as_ram.S ifeq ($(CONFIG_BINARYPI_LEGACY_WRAPPER), y) romstage-y += romstage.c -- cgit v1.2.3